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Found 2 results

  1. Hello, I downloaded the verilog source files for a H.264 Decoder from opencores.org; I'm trying to integrate this decoder into a video pipeline on a Digilent Zybo board. However, when I try to package this IP in Vivado 2016.2, the GUI shows there is no ports. I'm able to successfully package it, but it is useless because there is no i/o. I've attached a few pictures from the Create and Package IP wizard to illustrate what I'm talking about. If I click the port import dialog, as shown in the picture, nothing happens. Does anyone have any suggestions as to how I can successfully impor
  2. Hi, I am trying to generate a project from Digilent's GitHub. I followed this following manual: 1) https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-user-demo/start 2) https://reference.digilentinc.com/learn/software/tutorials/vivado-projects-from-digilent-github/start?redirect=1id=vivado/github so, When I execute the command "source ./create_project.tcl" according to the manual link 2, it gives me following error messages: "ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.2> of Vivado. Please run