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Found 2 results

  1. Hello, I hope you will be enjoying your vacations if you have been given some. For me this has meant finally being able to work on my spare-time experiment and finally reach closure on my upgraded design. Let me describe the process. The ArtyZ7-20 is just the initial prototyping. I'm going to move to real production FPGA boards ASAP (probably in August) but for the time being I'd just want to go ahead with the Arty. The system is systemverilog RTL and barebone C++. The initial design was 100Mhz and 6-stage pipe. Vivado estimated about 2.2W power. I suspect it was much lo
  2. Hi Im using Zybo 7020 Vivado/Vitis 2020 and i have some errors on Vitis when i compile the hw platform. "Running Make libs in ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src" make -C ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta rtfiles -g -Wall -Wextra" make[2]: Entering directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/PmodGYRO_v1_