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Found 34 results

  1. Hi, I'm new to this. I want to know how to describe in VHDL the operation of the ADC of the Nexys 4 to view it in LEDs. Any suggestion?
  2. Hello, some people might already know The PoC-Library. It's a collection of over 120 free and open source IP cores, that are platform independent. The IP core work on Altera, Intel, Lattice and Xilinx FPGAs of any device family. The core are describe in platform independent, generic VHDL code. If vendor primitives are required or better implementations can be achieved, a configuration mechanism will select a suitable implementation. PoC has gotten a first simple set of new I/O controllers abstracting Digilent's Pmods. These are located here: I might wonder if users in this forum or Digilent itself would be interested to add more Pmod abstraction layers for modules like the temperature sensor, OLED displays, ... I'm going to release a set of basic I/O controllers for I²C, OW and SPI soon. These can then be used as a communication base for higher level protocol implementations to the Pmods. If one is interested or has questions, please let me know. You can contact me e.g. via Gitter: Kind regards Patrick Lehmann
  3. create sine wave on dac using vhdl

    i want to generate sine wave on dac (pmodda3)( i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;
  4. Not understanding LCD Display

    Hello Digilent community, I am currently taking my first digital electronics class and my final project is a calculator written in VHDL using a Basys3 board, 16-key keypad, and a 16x2 LCD display with parallel interface, all provided by Digilent. I took a look at the provided example code from the resource library and I just had some questions about how it works. Now, the example code declares a constant before any of the processes, and this constant is an array of std_logic_vectors so it holds a preloaded message "Hello From Digilent" with the necessary function sets and all that preceding the message. In my case, I have to have a way to display the inputs from the keypad on the display and also display the output on the 2nd line of the display. I have the main logic part of the calculator settled, I just want to know how I can direct these signals from the keypad and the output of the computational module (as in the sum, difference, product, etc.) to the LCD display. I have never played with a display before now and never used VHDL or any type of board like the Basys3 before this class, so I guess I'm still quite novice and don't understand a good part of what the example code is telling me. I do get that the state machine is just cycling through the values in the constant and waits for certain delays to pass through before transitioning between certain states. Since the values on the display have to be updated live as the user inputs numbers from the keypad and also when there is a value computed, how can I shift from having a constant with a preloaded message to something that can update itself as needed? My idea was keep the idea of the array of std_logic_vectors but only have one value (rather than the 23 or 24 that are preloaded in the current example code) that will update with every key press. I'll have two of these, one for the inputs (to show the numbers and operations on the first line) and one for the output (to show on the second line). I'm thinking maybe I declare a variable within a process that will update and be sensitive to the key presses? Also, I tried looking around the reference manual and such but I could not find the function code for how to display information on the 2nd line; so far, stuff only displays on the first line. Sorry this is such a bulky post. I have had a lot of questions and my professor hasn't been around much. Also, part of this project is learning to interface with new components, so in my case the keypad and lcd display, and I'm not having much luck without any guidance unfortunately. Thank you for taking the time to read this! P.S. Attached the example vhd file from Digilent here for easy access in case anyone wants to look! PmodCLP.vhd
  5. Nexys_Video_Vivado2014_PmodDA4

    Hello, dear collegues! I work with Nexys Video board. I use VHDL. Now I try to create project with PmodDA4. I have 4 variables which I obtained inside the project and I want to obtain it like 4 analog signals. I have found an example, but when I tried to implement it for my board it does not work (code is bellow)... If it is some example code for this PmodDA4, please send it... I could not find it for this board. -- The four left-most switches (SW15-SW12) define the command, i.e. 0011 -- The four switches after (SW11-SW8) define the address, i.e. 1111 -- The right-most switch (SW0) defines the regime: working, fast (0) or "human", slow (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity pgnd is port( btnc : in STD_LOGIC; sysclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(3 downto 0); jb : out STD_LOGIC_VECTOR(3 downto 0) ); end pgnd; architecture pgnd of pgnd is signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0, pout: STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk, btnc) begin if btnc = '1' then count <= X"0000000"; elsif rising_edge(sysclk) then count <= count + 1; end if; end process; sclkp: process(sysclk, count, btnc) begin if btnc = '1' then sclk0 <= '0'; elsif rising_edge(sysclk) then if sw(0) = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process; -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0, btnc) begin if btnc = '1' then word_count <= "101000"; -- # 40 elsif rising_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process; -- Sync signal signal_syncp: process(sclk0, word_count, btnc) begin if btnc = '1' then sync0 <= '1'; elsif rising_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process; signal_shiftp: process(sclk0, word_count, sw, count2, btnc) begin if btnc = '1' then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; elsif rising_edge(sclk0) then if word_count = "101000" then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process; -- Sawtooth data modulation data_countp: process(sclk0, word_count, btnc) begin if btnc = '1' then count2 <= X"001"; elsif rising_edge(sclk0) and word_count = "101000" then count2 <= count2 + 1; end if; end process; -- Data transmission process spip: process(sclk0, word_count, btnc) begin if btnc = '1' then pout <= '0'; elsif rising_edge(sclk0) then -- Send the signal pout <= pdata(31); end if; end process; JB(0) <= sync0; -- SYNC JB(1) <= pout; -- DOUT JB(2) <= pout; -- Just duplicate DOUT JB(3) <= sclk0; -- SCLK led(0) <= sclk0 when sw(0) = '1' else -- show the real SCLK count(24); -- or indicate device is working on higher freq led(1) <= sclk0 when sw(0) = '1' else not count(24); -- Couple the other leds only if the frequency is "human" led(2) <= pout when sw(0) = '1' else '0'; -- DOUT led(3) <= sync0 when sw(0) = '1' else '0'; -- SYNC end pgnd;
  6. Ethernet UDP echo-server

    A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use any input or output FIFO's as elesticity buffers,both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes, which allows better resource utilisation at the price of, probably, more complex design architecture. Design is implemented in VHDL using ISE by Xilinx. Below there are the source files for the echo-server projects along with .m file to transmit/receive data using MatLAB. Figure "wireshark_capture" illustrates the data traffic between FPGA board and data server (MatLAB); Figure "TxRx_Error" compares transmitted data against the data received from the board. UDP echo-server manual.7z UDP echo-server.7z
  7. BASYS3 VGA Output Out of Range problem

    Hello everyone, I just started learning VHDL and digital design on my college and as a term project I am to design a digital circuit which will output a game through VGA pins. I first started examining examples on the internet and tried to synthetise myself on Vivado Design Suite. However, I encountered problems. The following is the code which I use to synchronize image. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sync_module is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; start : in STD_LOGIC; y_control : out STD_LOGIC_VECTOR (9 downto 0); x_control : out STD_LOGIC_VECTOR (9 downto 0); h_s : out STD_LOGIC; v_s : out STD_LOGIC; video_on : out STD_LOGIC); end sync_module; architecture Behavioral of sync_module is -- Video Parameters constant HR:integer:=1280;--Horizontal Resolution constant HFP:integer:=48;--Horizontal Front Porch constant HBP:integer:=248;--Horizontal Back Porch constant HRet:integer:=112;--Horizontal retrace constant VR:integer:=1024;--Vertical Resolution constant VFP:integer:=1;--Vertical Front Porch constant VBP:integer:=38;--Vertical Back Porch constant VRet:integer:=3;--Vertical Retrace --sync counter signal counter_h,counter_h_next: integer range 0 to 799; signal counter_v,counter_v_next: integer range 0 to 524; --mod 2 counter signal counter_mod2,counter_mod2_next: std_logic:='0'; --State signals signal h_end, v_end:std_logic:='0'; --Output Signals(buffer) signal hs_buffer,hs_buffer_next:std_logic:='0'; signal vs_buffer,vs_buffer_next:std_logic:='0'; --pixel counter signal x_counter, x_counter_next:integer range 0 to 900; signal y_counter, y_counter_next:integer range 0 to 900; --video_on_off signal video:std_logic; begin --clk register process(clk,reset,start) begin if reset ='1' then counter_h<=0; counter_v<=0; hs_buffer<='0'; hs_buffer<='0'; counter_mod2<='0'; elsif clk'event and clk='1' then if start='1' then counter_h<=counter_h_next; counter_v<=counter_v_next; x_counter<=x_counter_next; y_counter<=y_counter_next; hs_buffer<=hs_buffer_next; vs_buffer<=vs_buffer_next; counter_mod2<=counter_mod2_next; end if; end if; end process; --video on/off video <= '1' when (counter_v >= VBP) and (counter_v < VBP + VR) and (counter_h >=HBP) and (counter_h < HBP + HR) else '0'; --mod 2 counter counter_mod2_next<=not counter_mod2; --end of Horizontal scanning h_end<= '1' when counter_h=799 else '0'; -- end of Vertical scanning v_end<= '1' when counter_v=524 else '0'; -- Horizontal Counter process(counter_h,counter_mod2,h_end) begin counter_h_next<=counter_h; if counter_mod2= '1' then if h_end='1' then counter_h_next<=0; else counter_h_next<=counter_h+1; end if; end if; end process; -- Vertical Counter process(counter_v,counter_mod2,h_end,v_end) begin counter_v_next <= counter_v; if counter_mod2= '1' and h_end='1' then if v_end='1' then counter_v_next<=0; else counter_v_next<=counter_v+1; end if; end if; end process; --pixel x counter process(x_counter,counter_mod2,h_end,video) begin x_counter_next<=x_counter; if video = '1' then if counter_mod2= '1' then if x_counter= 639 then x_counter_next<=0; else x_counter_next<=x_counter + 1; end if; end if; else x_counter_next<=0; end if; end process; --pixel y counter process(y_counter,counter_mod2,h_end,counter_v) begin y_counter_next<=y_counter; if counter_mod2= '1' and h_end='1' then if counter_v >32 and counter_v <512 then y_counter_next<=y_counter + 1; else y_counter_next<=0; end if; end if; end process; --buffer hs_buffer_next<= '1' when counter_h < 704 else--(HBP+HGO+HFP) '0'; vs_buffer_next<='1' when counter_v < 523 else--(VBP+VGO+VFP) '0'; --outputs y_control <= conv_std_logic_vector(y_counter,10); x_control <= conv_std_logic_vector(x_counter,10); h_s<= hs_buffer; v_s<= vs_buffer; video_on<=video; end Behavioral; ...and the following is a snippet from my constraints file : set_property PACKAGE_PIN N19 [get_ports {rgb[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] set_property PACKAGE_PIN J18 [get_ports {rgb[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] set_property PACKAGE_PIN D17 [get_ports {rgb[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] set_property PACKAGE_PIN P19 [get_ports h_s] set_property IOSTANDARD LVCMOS33 [get_ports h_s] set_property PACKAGE_PIN R19 [get_ports v_s] set_property IOSTANDARD LVCMOS33 [get_ports v_s] ## END VGA CONNECTOR I went through google results for this "out of range" problem and none of them solved my problem. Then I connected my oscilloscope to the output of the horizontal sync and vertical sync. This is from the 13 pin of the VGA output : And this is the output of the 14. pin: So what do you think my problem is? The default demo on BASYS3 runs flawlessly.
  8. arty - getting started and above

    Hi, I'm looking for tutorials to handle the arty board. I allready keept an eye on the digilent examples. But I want a fast aproach with examples like this Knows anybody good online resources to learn step by step how to create UART, SPI, I2C, analog dataloger (yes, i know, there is a XADC-sheet from digilent), ditgital datalogger, and so on?
  9. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  10. XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================
  11. VHDL read from BRAM

    Hi, I have a block design with a microblaze, a BRAM, and a custom ip (VHDL). With the custom IP, I have 4 separate signals that will read at the same time from 4 consecutive rows in the bram and output the values. I'm having trouble figuring out how to read 4 separate signals from a single BRAM at the same time. Any advice is much appreciated. Thanks, Vic
  12. Custom Function Generator

    This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  13. We need a noisy sine wave signal. We have generated the sine wave(using VHDL), but we cant figure out how to add noise to it. We are including the code for sine wave generation. Kindly mention how to add Gaussian/any other noise to it. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible. entity sine_wave is port (clk :in std_logic; data_out : out STD_LOGIC_VECTOR(7 downto 0) ); end sine_wave; architecture Behavioral of sine_wave is signal i : integer range 0 to 29:=0; --type memory_type is array (0 to 29) of integer; type memory_type is array (0 to 29) of std_logic_vector(7 downto 0); --ROM for storing the sine values generated by MATLAB. signal sine : memory_type :=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101", "00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101"); --hi begin process(clk) begin --to check the rising edge of the clock signal if(rising_edge(clk)) then data_out <= sine(i); i <= i+ 1; if(i = 29) then i <= 0; end if; end if; end process; end Behavioral;
  14. PMOD AD1 on Nexys4

    Hi, I recently purchased a nexys 4 board and a Pmod AD1 to get short latency audio input to the fpga. Is there any vhdl example available to get audio samples from the AD1? the Digilent ressource center does not have any ... thanks, Pierre
  15. Create a Variable Duty Cycle using VHDL

    Hello, How to generate a variable duty cycle from this code? This code is for 10% duty cycle, 500 Hz frequency, but I want to generate 10%, 30%, 50%, 70% and 90% duty cycle. The clock frequency is 50 MHz. I want to generate a variable duty cycle from 5 variable frequency which are 500 Hz, 1 kHz, 50 kHz, 500 kHz, and 1 MHz. Please someone help me. I need your help. Thank you. DutyCycle(500Hz-10%).vhd DutyCycle500Hz_tb.vhd
  16. VHDL - 10% duty cycle

    Hello, I'm new to VHDL. I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. FreqDivider500Hz.vhd
  17. 3 bit output

    Hello, I need to design 3 bit output, which are 000, 001, 010, 011, 100 using FPGA. I'm using VHDL language. I have already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you. selectsig.vhd selectsig_tb.vhd simulator.wcfg
  18. 8x1 multiplexer

    Hello, I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it? I'm using Xilinx and the language I used is VHDL. Here I attach a picture. Please help me. Thank you.
  19. MUX 2x1 using VHDL

    Hello, I need to design PWM for a multiplexer 2x1 for my project. The description is: If select = 0, output = input 1 (10kHz) If select = 1, output = input 2 (100kHz) The problem is, I don't know how to implement that frequency in my coding. Is it possible to do that. If yes, how making it? Someone please help me. Here, I attach my code. mux2to1.vhd mux2to1_tb.vhd Thank you.
  20. Frequency Divider using VHDL

    Hello, I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? This is for the code,FreqDivider.vhd and this is for testbench, FreqDivider_tb.vhd. Thanks.
  21. I've been playing around with a sub-$10 6-axis gyro/acceleration/attitude sensor (from with my Basys3 (and my Raspberry Pi Zero). The sensor reports over RS232 at 115200 making it far easier to decode than with sensor that speak I2C. The short video at shows as the senor reads from -1G (approx 0xEFFF) to +1G ( approx 0x1000) as the sensor is rotated in the Y axis. Source can be found at
  22. I am a sophomore in an electrical engineering program, and I would like to know what software I need for your starter kit/boards priced between 0 and $300. The boards and software must run on Windows 10 Pro and use VHDL. Note that Xilinx (Vivado) does not work on this computer; I don’t know why. As an FYI, my school uses the BASY 3, Artix-7 FPGA. Something similar to this would be appreciated. Thanks
  23. I realize I only know a tiny corner of all of VHDL. I know little about creating packages, libraries, other data types outside of 'std_logic' and 'signed', 'unsigned', 'integer' and 'natural', things like "a <= b after 10 ns;", string handling, file handling, structures, text I/O ..... the list goes on and on. Just how much of VHDL do you need to work with FPGAs? My guess is about 20% And once you get that far, is it worth learning more? And is Verilog the same? And does anybody have any recommended resources on more advanced VHDL?
  24. Working with DA4 PMOD on Nexys4

    Hello! I have created some VHDL code (attached) to test if DA4 convertor works. The simulation reveals no problems with timing of SCLK, DATA and SYNC channels according to the AD5628 data sheet, however output of the eight out data pins of DA4 does not work. Basically I am trying to send the the data to JB PMOD. Command and address are tuned by the eight switches on the Nexys4. The used command is 0011 and the address is 1111 (is that correct, by the way?), but I have tried plenty of other commands. Still the problem persists — no out data from DA4. Please do not hesitate asking for additional information. Thank you for your help. pmod.vhd.txt