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Found 61 results

  1. Hello, I have a PmodOLED connected to Nexys 3 board and so far I was able to display ASCII characters by using either the VHDL example code provided by Digilent or the code from Mr. Y.Borrnat from here. I would like to display bitmap graphics. Could you guide me a little? Is it possible to do that by altering one of the codes mentioned? PS: I found a video unfortunatelly without any comments, so I mean something like that or draw a chart perhaps. Thank you.
  2. Hello, I am trying to send a character to FPGA from PC hyper terminal , for eg : 's' to start other processes in FPGA like initiating generation of CCD signals and sampling ADC et al and a different ascii character to stop the processes. I am able to send a ASCII character from PC hyper terminal and receive binary value it on FPGA LED's however I'm unable to use this for control. Please find my top level code below. 'Start' signal is to be controlling the initiation of other processes. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; use IEEE.MATH_REAL.ALL; ----------------------------------------------------- entity top_module is port( --------------------UART_GUI------------------------------- RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); ---COMMON INPUTS--- clk, rst : in std_logic; --send_ccd : in std_logic;---------------CCD control SH,ICG,master_ccd_clock : out std_logic; ----FOR AD7980-------- --sample: in std_logic; -------------- to start sampling samp_ind: out std_logic;---------------indicates sampling in process adc_cnv : out std_logic;---------------cnv for AD7980 adc_clk : inout std_logic;--------------SPI clock adc_miso : in std_logic;------------------output from AD7980 -------FIFO SIGNALS-------- WriteEn , ReadEn : in std_logic; -------------fifo controls full, empty : out std_logic ------------------indicates fifo status ); end top_module; architecture structural of top_module is ----------------------------------------------------------------------------UART CONTROL GUI------------------------------------- component receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END component receiver; ----------------------------------------FIFO COMPONENT DECLARATION ----------------------------------------------------------------- component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; -------------------------------------------------------------------------------------------------------------------------- signal fifo_data_out : STD_LOGIC_VECTOR (15 downto 0); signal adc_out : std_logic_vector(15 downto 0); signal start :std_logic; -------------------------UART_RX_FOR CONTROL_ OF_PROCESSES--------------------------------------------------------------- process(Clk,RxData) begin if RxData = "01110011" then start <= '1' ; elsif RxData = "01110000" then start <= '0'; else start <= '0'; end if; end process; --------------------AD7980PORTMAP---------------------------------------------------------------------------------- AD7980 : entity work.AD7980 port map ( clock => clk, sample => start, -- data output Dout => adc_out(15 downto 0), samp_ind => samp_ind, -- ADC connection adc_miso => adc_miso, adc_cnv => adc_cnv, adc_clk =>adc_clk ); ---------------------------------------------FIFO PORTMAP---------------------------------------------------------------- fifo_i: component fifo port map ( clk_100MHz => clk, din_0(15 downto 0) => adc_out(15 downto 0), dout_0(15 downto 0) => fifo_data_out(15 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); ccd_control : entity work.TCD1103GFG port map ( clock => clk, send => start, SH => SH, ICG => ICG, master_ccd_clock => master_ccd_clock); ---------------------------------------------------------------UART GUI CONTROL--------------------------------------- uart_gui : entity work.receiver port map ( clk => clk, reset => rst, RxD => RxD, RxData => RxData ); end structural; Here is the UART receiver open source code I'm using that works LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END receiver; ARCHITECTURE behavioural OF receiver IS SIGNAL shift : STD_LOGIC; SIGNAL state : STD_LOGIC; SIGNAL nextstate : STD_LOGIC; SIGNAL bitcounter : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL samplecounter : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL counter : STD_LOGIC_VECTOR(13 DOWNTO 0); SIGNAL rxshiftreg : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL clear_bitcounter : STD_LOGIC; SIGNAL inc_bitcounter : STD_LOGIC; SIGNAL inc_samplecounter : STD_LOGIC; SIGNAL clear_samplecounter : STD_LOGIC; constant clk_freq: integer := 100000000; constant baud_rate :integer := 9600; constant div_sample :integer := 4; constant div_counter :integer := (clk_freq/(baud_rate*div_sample)); constant mid_sample : integer := (div_sample/2); constant div_bit : integer := 10; BEGIN RxData <= rxshiftreg(8 DOWNTO 1); PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN state <= '0'; bitcounter <= "0000"; counter <= "00000000000000"; samplecounter <= "00"; ELSE counter <= counter + "00000000000001"; if (counter>= div_counter - 1) then counter <= "00000000000000"; state <= nextstate; IF (shift = '1') THEN rxshiftreg <= (RxD & rxshiftreg(9 DOWNTO 1)); END IF; IF (clear_samplecounter = '1') THEN samplecounter <= "00"; END IF; IF (inc_samplecounter = '1') THEN samplecounter <= samplecounter + "01"; END IF; IF (clear_bitcounter = '1') THEN bitcounter <= "0000"; END IF; IF (inc_bitcounter = '1') THEN bitcounter <= bitcounter + "0001"; END IF; END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN shift <= '0'; clear_samplecounter <= '0'; inc_samplecounter <= '0'; clear_bitcounter <= '0'; inc_bitcounter <= '0'; nextstate <= '0'; CASE state IS WHEN '0' => IF (RxD = '1') THEN nextstate <= '0'; ELSE nextstate <= '1'; clear_bitcounter <= '1'; clear_samplecounter <= '1'; END IF; WHEN '1' => nextstate <= '1'; IF (samplecounter = (mid_sample - 1)) THEN shift <= '1'; END IF; IF (samplecounter = (div_sample - 1)) THEN IF (bitcounter = (div_bit - 1)) THEN nextstate <= '0'; END IF; inc_bitcounter <= '1'; clear_samplecounter <= '1'; ELSE inc_samplecounter <= '1'; END IF; WHEN OTHERS => nextstate <= '0'; END CASE; END IF; END PROCESS; end behavioural; I'm unsure if the issue is because of the number of clock cycles for which the character 's' exists. Please help me understand the miss here.
  3. Hi, I want to use the DD to test an ASIC which needs quite some complicated digital control. First the ASIC needs to be initialized with several SPI commands. Once the device is configured a test sequence (4 digital control lines) will trigger the ASIC and thereby acquire measurement data. At last this data need to read out. I was wondering, if I could use the patterns which are generated by our (VHDL) simulator as input to the DD. Is there a script which can read the vcd-files and Importes them to WaveForms? As I am quite new to this field, I do not have any expierence with JavaScript or Phyton (but willing to learn )
  4. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf
  5. Junior_jessy

    Voice-activited

    Hello, I'm trying to make a voice-activated on a nesys4 and i want to use the pmodMic3.To do si, I want to use the SPI protocol but i don't know how. So how can i choose the SPI protocol ? Furthermore, I got some issues when filling in the constraint's file. On the web-site of Diligent, the pin2 is not connected but, the protocol SPI show the opposite. So how to Well connect the in/out of the peripheral to the board in the constraint's file? Thank you in advance for your answer. Junior
  6. I am new in VHDL and have a school project. I am reading 40-bit data from DHT11 humidity sensor. Although first 8 bit is meaningful to me, I read all 40. At the end of the transaction, it is required to light 8 LEDs corresponding to each bit of 8bit. I can light the confirmation LED which lights when all 40-bit data is received. But, can’t do it for the data LEDs. I need urgent help. Thanks.
  7. I have connected an ov 7670 camera to my Basys 3 board and want to transmit the frame to a PC via the micro-usb port. I have tried UART serial communication, but the bit per second rate is simply not high enough to transmit a full 640 * 480 frame 15/30 times a second. I had the idea of implementing some sort of parallel communication, however I could not find any information or guides. I was wondering if anyone could help me out either with parallel communication, or suggesting a different method of transmitting frames to a PC. Thanks in advance.
  8. Hi, I have started using PMOD BLE recently and I can make a connection in between BLE and PC using a terminal (with Nexys4DDR making a direct connection in between). However, when I write a VHDL code, describing what I made on the terminal one by one, the BLE device stucks at rebooting. For both applications I use the following sequence that is described in "RN4871_user_guide.pdf" page 59 : - Send $$$ - Wait a second - Send SS,40<CR> (this is to select UART Transparent feature only) - Wait a second - Send R,1<CR> - Wait a second - Wait for an ASCII entry but, at "R,1<CR> ", the BLE device turns the blue LED on (which is LD1 on schematic) and it does not shuts it off no matter what. While so, (I mean when the LED is ON) the iOS application SmartDiscover (or anyother terminal) cannot see the module. So, I cannot reach the device at all. Besides, the device returns this when connected via PC terminal (through cable) => CMD> AOK<\r><\n>CMD> Rebooting<\r><\n>%REBOOT% and returns this when FPGA communicates with the device directly => CMD> AOK<\r><\n>CMD> Rebooting<\r><\n> so, it does not return me %REBOOT% string, but seems like it stucks at some point where it is trying to reboot itself. Any help with this would be very nice at this point, Thanks in advance, Bera
  9. Hi, guys, I am in need of a Digilent board to run Linux with a GUI to have access to IOpins and peripherals, and also to work together with the vhdl codes on the FPGA. I am not sure how to install Linux on SD card, start a boot from there, ANDhave at the same time a vhdl code running on FPGA that I could edit and compile using the vivado (2018.2). The idea is to have the vhdl code running the hardware and the GUI on linux to present values of input, output, make the configuration on-line of the vhdl variables, etc... I was thinking about the Zybo board. Can someone give me, please, some directions and/or suggestions? Regards,
  10. macellan

    XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================
  11. This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  12. Hi all, I am doing a project on vhdl in which i am trying to display a pattern (like forming an eight) on seven segment display on spartan 3 fpga kit.I have written the vhdl code and simulation works correctly,but the problem is i am not able to write the ucf code (written but may be wrong) required for implementation on spartan 3 kit.I would highly greatful if anyone can help me as to how to write ucf code or modify my vhdl code. Thanks in advance. Regards, Nikhil Singh pattern generator.txt
  13. Nikhil Singh

    FPGA projects

    Can anyone suggest me some good beginner level projects which i can implement on spartan 3 fpga kit using VHDL. I have some projects in mind like the implementation of 8-bit microcontroller in fpga. But is the project too complex is think.It would be great if anyone can suggest me how to begin.Thanks in advance.
  14. Greetings. I just started out VHDL not long ago,and not quite familiar with Moore FSM. So I was trying to write this Moore FSM code as shown in Picture of my initial sketch(Link to imgur,safe to click). after search for some reference about Moore in VHDL,I'm still stuck. I'm hoping someone can help me fill-in the missing pieces of my code and to fit into the sketch. Sincerely Appreciate. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity M6B is Port ( clk : in STD_LOGIC; x : in STD_LOGIC; rst : in STD_LOGIC; --z : out STD_LOGIC_VECTOR (6 downto 0); AN : out STD_LOGIC_VECTOR (1 downto 0); ledout : out STD_LOGIC_VECTOR (6 downto 0)); end M6B; architecture Behavioral of M6B is type state_type is (s0,s1,s2,s3,s4,s5); signal state : state_type; signal ledbcd : std_logic_vector (3 downto 0); signal ledonc : std_logic_vector (1 downto 0); signal osc : STD_LOGIC_VECTOR (24 downto 0); signal refresh_counter: STD_LOGIC_VECTOR (16 downto 0); signal oscen : std_logic; signal dispn : std_logic_vector (6 downto 0); begin process (clk,rst) begin if rst = '1' then state <= s0; elsif (rising_edge(clk)) then case state is when s0 => if x = '0' then state <= s1; else state <= s0; end if; when s1 => if x = '0' then state <= s2; else state <= s1; end if; when s2 => if x = '0' then state <= s3; else state <= s2; end if; when s3 => if x = '0' then state <= s4; else state <= s3; end if; when s4 => if x = '0' then state <= s5; else state <= s4; end if; when s5 => if x = '0' then state <= s0; else state <= s4; end if; end case; end if; end process; process (state) begin case state is when s0 => AN <= "10"; ledout <= "0000000"; when s1 => AN <= "10"; ledout <= "0000111"; when s2 => AN <= "10"; ledout <= "0000000"; when s3 => AN <= "10"; ledout <= "1001111"; when s4 => AN <= "10"; ledout <= "0000000"; when s5 => AN <= "10"; ledout <= "0000111"; end case; end process; end Behavioral;
  15. DigitalConfig

    Array

    I have found online lots or resources for creating arrays of signals, but what I have is the need to create an array of processes. for example I have a simple process that adds 2 8bit signals: sigT <= sig1 + sig2; I would like to create an Array of a particular circuit design where I could use dozens, perhaps 100s and if I am able to upgrade to your Artix200 or kintex products soon perhaps 1000s. can you direct me to such resources that might lead me to complete this kind of task please? Sincerely, DC
  16. hello, I am interested in the following reference design: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-vga-test-pattern-with-mouse-overlay/start The design currently does not provide any sources: Is this project abandoned? I believe it had not been updated since 2015. Is there a later version available (this one, perhaps, or on github?) I am interested in the USB host with mouse, which I intend to implement on the Zybo/Zybo-Z7. Do you provide the sources for this project? Is there a project you can recommend, There is also the BIST for the Zybo-Z7, maybe it contains relevant references? thank you
  17. To control the 4 digit seven segment LED's on the Basys3 I need to mux the data by controlling the anode signal. I made a counter: (possibly a terrible resource hungry counter) seg_mux_clk: process(clk_240)--cycle through the 4 sev seg displays begin if rising_edge(clk_240) then cnt <= (cnt + 1)mod 4; end if; end process; next I have my one hot logic which I have recently decided to change. I have nothing to back this up but I suspect that the FPGA can more easily handle shifting a bit than it could handle multiplying a number. Believing the shift requires less logic also makes me think its overall better for timing. What you do you guys think? old version: an_i <= not std_logic_vector(to_unsigned(2 ** cnt,an_i'length)); New version: an_i <= not std_logic_vector(shift_left(to_unsigned(1,an_i'length) ,cnt)); PS if you are wondering why I don't just have a process that uses cnt as an unsigned, set cnt to 1 and mulitply it by 2 each clock cycle (1,2,4,8,1,2,4,8,....) , its because my displayed data is an array. This keeps my data and the proper seven segment in sync. seven_seg_out_reg: process(clk_240) begin if rising_edge (clk_240) then seg <= display(cnt); an <= an_i; end if; end process;
  18. on a simple design that adds or subtracts button presses on a basys3, I have the counter signal set as an integer from 0 to 7. When implementing this design it performs as expected. When counting up or down the 7 segment display goes from 7 back to 0 or from 0 to 7 when exceeding the integer range of the counter. When running this design in the behavioral simulation, the range is ignored. Counting from 0 to (-1) does not show a value of 7 but that of a 32 bit vector of all 1's. (negative 1) Thoughts?
  19. I have built a very simple test case, built for a Basys3, in an effort to isolate my mental error. In the VHDL below I am expecting that the process(btn) will only be triggered when the input "btn" changes. The ila I have in place shows that the process is running continuously. Well at least that is what I think it is showing me. The ila shows "btn" signal remains at zero while the up_test is increasing at a rate that appears to be free running. I must have some horrible misunderstanding about the behavior of a process with respect to its sensitivity list. Please set me straight. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity btn_test is Port ( clk_100M : in STD_LOGIC; btn : in STD_LOGIC_VECTOR (4 downto 0); led : out STD_LOGIC_VECTOR (15 downto 0); seg : out STD_LOGIC_VECTOR (6 downto 0); an : out STD_LOGIC_VECTOR (3 downto 0); dp : out STD_LOGIC ); end btn_test; architecture Behavioral of btn_test is signal up_test : natural := 0; signal up_test_i : std_logic_vector (31 downto 0); COMPONENT ila_0 PORT ( clk : IN STD_LOGIC; probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); probe1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT ; begin up_test_i <= std_logic_vector(to_unsigned(up_test,32)); up_test_ila : ila_0 PORT MAP ( clk => clk_100M, probe0 => up_test_i, probe1 => btn ); count_button_process_triggers: process(btn) begin up_test <= up_test +1; end process; led <= (others => '0'); seg <= (others => '0'); an <= (others => '1'); dp <= '0'; end Behavioral;
  20. Greetings fellow FPGA enthusiasts! I'm looking for eyeballs Specifically digital logic enthusiasts, HDL or otherwise, and maybe even those appreciative of retrocomputing (my first Zybo project is a C64 clone after all). It is my hope I might find some people interested in this project: https://github.com/gau-veldt/InsideTheBox and perhaps also the associated "Inside the Box" YouTube channel https://www.youtube.com/channel/UCnVbLwPm8Rrd8YP44djBfoQ where I am going to attempt to explain aspects of the project to others attempting to learn. I'd like to break that feeling that I'm the only one in the world interested in these things (I know I'm not but experience and YT video visitor stats keep trying to tell me otherwise ).
  21. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  22. Hello! For a (very modest) first try with the BASYS 3 board, I'd like to measure a signal using an ADC for the BASYS 3 board I have, possibly average the signal over a set of measurements and then send this out using PWM. I'm looking for examples in VHDL, and only found one in verilog so far. And any explanation that you care to offer me. As you can tell I'm a novis and a biologist at that. I've taken (75%) of a beginners course in VHDL, but am very interested and enthusiastic. Now, hit me (with kid gloves). Thanks in advance!
  23. Hi all, A new website is offering FPGA projects and ZYNQ step by step tutorials with full source codes, maybe it is useful : https://www.fpgagate.com/
  24. Hello everyone, I'm using Zybo and i want to create a custom ip. The ip will have two inputs (as registers) that has 32 bits: Let's call them a[31:0] and b[31:0]. And i want to get memory value at a and add b. The calculated value is a new memory address and i want to read value at that address and write it into the third register of ip. But i haven't find a tutorial like this. If there's any, i would like to know it. Thanks for your time.
  25. Hey everyone, I've done the initial design of a register file (16x 32-bit registers, two write ports, four read ports) in VHDL as part of a larger project, but seeing as I am a relative newcomer to HDLs, I was hoping to get some feedback on my design, any errors I may have made, or any improvements I might want to make. Here is the VHDL: -- Register file -- Two write ports, four read ports. -- For performance reasons, this register file does not check for the same -- register being written on both write ports in the same cycle. CPU control -- circuitry is responsible for preventing this condition from happening. library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; use work.func_pkg.all; entity registerFile is port ( clk : in std_logic; rst : in std_logic; writeEnableA : in std_logic; writeEnableB : in std_logic; readSelA, readSelB, readSelC, readSelD, writeSelA, writeSelB : in std_logic_vector(3 downto 0); data_inA, data_inB : in std_logic_vector(DATA_WIDTH - 1 downto 0); data_outA, data_outB, data_outC, data_outD : out std_logic_vector(DATA_WIDTH - 1 downto 0) ); end registerFile; architecture behavioral of registerFile is type regArray is array (0 to 15) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal registers : regArray := (others => (others => '0')); begin data_outA <= registers(to_integer(unsigned(readSelA))); data_outB <= registers(to_integer(unsigned(readSelB))); data_outC <= registers(to_integer(unsigned(readSelC))); data_outD <= registers(to_integer(unsigned(readSelD))); registerFile_main : process(clk) begin if(rising_edge(clk)) then if(rst = '1') then registers <= (others => (others => '0')); else if(writeEnableA = '1') then registers(to_integer(unsigned(writeSelA))) <= data_inA; end if; if(writeEnableB = '1') then registers(to_integer(unsigned(writeSelB))) <= data_inB; end if; end if; end if; end process; end behavioral; This design is intended for use on FPGAs, hence the use of default values for the registers. I appreciate any feedback you might have! Thanks, - Curt