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Found 73 results

  1. MoGamaal

    Pmod OledRGB

    I think my question is general but i want to know how to initialize Pmod OledRGB using case when-statment i found some vhdl codes using this method but i cant understand it
  2. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  3. Hello everyone, I’m a newbie on working on zedboard, and I want to use my Zedboard to communicate with Pmod MIC3 this time. I did a few researches about how to use the Pmod MIC3, and I think I found something useful in another post, link: I’m really appreciate and thanks for their help, but unfortunately I still have no idea of how to make my Pmod MIC3 to run with my Zedboard. I know Pmod MIC3 is using SPI communication protocol and I read what SPI is, link: But I’m not sure is that Quad SPI is the same as SPI in Zedboard. About the Pmod MIC3, I know that it used a MEMS Mic and an ADC, but I also don’t know how to implement it, like do I need a code or IP cores to handle these 2 components? Here is a simply conclusion of my questions: 1. How to use SPI in Zedboard? (Any pin configuration is required?) 2. Do I need a code or something else to handle the ADC and MEMS Mic in Pmod MIC3? 3. Is it possible to make this project work in .vhdl? Or I need something else? 4. How to getting start with? 5. Importance of IP core I know IP cores is an important thing, but I don’t get a clear idea about it and how it works with Vivado. Any help and reference suggestions is appreciated! Thanks 😊 !!
  4. MoGamaal

    Display Variables

    I want to know how to display variables on PmodOLEDRGB from Sensors via artix-7 kit in vhdl
  5. Hi! I bought a Nexys 4 board and a Pmod OLED 128x32 screen, on which I am going to implement the Snake game, by programming the FPGA in VHDL. The problem that I encountered, is that I don't know how to set a pixel on the screen. I can only assume that I have to make some changes in the memory that maps the screen, something related to the example that I have found on the Pmod OLED's reference page, under the Example projects section. The given example takes a group of pixels and sends a character (its ASCII code), using the alphabet_screen variable, which is a memory. My question is, how should I write/ create the memory, in order for me to set only one pixel, not a group of them? Also, there is a charLib IP that is being used -- how can I export this from the example project, into my Snake project? Thank you!
  6. Hello, I new on Basys 3, and I need some examples for programming FPGA. In the resource center there are a lot of them, but the examples are written in verilog. I am using VHDL, so the questión is: Is there the same examples like the resource center written in VHDL?
  7. Hello! I have created some VHDL code (attached) to test if DA4 convertor works. The simulation reveals no problems with timing of SCLK, DATA and SYNC channels according to the AD5628 data sheet, however output of the eight out data pins of DA4 does not work. Basically I am trying to send the the data to JB PMOD. Command and address are tuned by the eight switches on the Nexys4. The used command is 0011 and the address is 1111 (is that correct, by the way?), but I have tried plenty of other commands. Still the problem persists — no out data from DA4. Please do not hesitate asking for additional information. Thank you for your help. pmod.vhd.txt
  8. Hello everybody, I want to implement a dac example into my fpga board (MYD-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.In other words, I try to implement LTC-2601 to 32 bit input. Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register (in this example slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only impulses. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some fluctuation in the wave. I leave my VHDL code below. Thank you. port( -- Users to add ports here output : out std_logic := '0'; -- User ports ends ); -- Add user logic here -- S_AXI_ACLK is the clock from Zynq-7000 Processing System IP. process(S_AXI_ACLK) variable index : integer := 0; variable counter: integer := 0; begin if rising_edge(S_AXI_ACLK) then case index is -- 4 Command Bits start when 0 => output <= '0'; when 1 => output <= '0'; when 2 => output <= '1'; when 3 => output <= '1'; -- 4 Command Bits end -- 4 Don't Care Bits start when 4 => output <= '0'; when 5 => output <= '0'; when 6 => output <= '0'; when 7 => output <= '0'; -- 4 Don't Care Bits end -- 16 Data Bits start when 8 => output <= slv_reg0(16); when 9 => output <= slv_reg0(17); when 10 => output <= slv_reg0(18); when 11 => output <= slv_reg0(19); when 12 => output <= slv_reg0(20); when 13 => output <= slv_reg0(21); when 14 => output <= slv_reg0(22); when 15 => output <= slv_reg0(23); when 16 => output <= slv_reg0(24); when 17 => output <= slv_reg0(25); when 18 => output <= slv_reg0(26); when 19 => output <= slv_reg0(27); when 20 => output <= slv_reg0(28); when 21 => output <= slv_reg0(29); when 22 => output <= slv_reg0(30); when 23 => output <= slv_reg0(31); -- Data Bits end when others => end case; if counter = 0 then index := (index + 1) mod 24; end if; counter:= ( counter +1) mod 20; end if; end process; -- User logic ends Note: This vhdl code is from my axi peripheral ip. The rest of the ports, entity, logic and etc is created by the ip itself. So I did not put them here.
  9. I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation. I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity? EDIT: Verilog module(originally a testbench for another project): module testoverlay_0( input wire rst_n, input wire clk, output reg[23:0] RGBOut, output reg HSync1, output reg VSync1 ); VHDL: component testoverlay_0 is port ( rst_n: in STD_LOGIC; clk: in STD_LOGIC; RGBOut: out STD_LOGIC_VECTOR ( 23 downto 0 ); HSync1: out STD_LOGIC; VSync1: out STD_LOGIC ); end component testoverlay_0; test_overlay: component testoverlay_0 port map ( rst_n => reset_1, clk => sys_clk_i_1, RGBOut(23 downto 0) => v_axi4s_vid_out_0_vid_io_out_DATA_1(23 downto 0), HSync1 => v_axi4s_vid_out_0_vid_io_out_HSYNC_1, VSync1 => v_axi4s_vid_out_0_vid_io_out_VSYNC_1 );
  10. Hello everyone I am a student in bachelors and I am working on a project combining Digital Image Processing and FPGA programming. The project consists of global image thresholding but should be done real-time by the FPGA and returning the output image back to PC/laptop. I have the Nexys Video board but I still haven't figured out how to "import" the images. Is it even possible to store data in the FPGA's buffer/RAM? If someone could help me with importing/exporting data I would be very grateful. My course in FPGA includes programming in VHDL instead of Verilog, so that's the one I am using. Every information would be helpful.
  11. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port( clk : in std_logic; rst : in std_logic; start : in std_logic; input : in std_logic_vector(7 downto 0); done : out std_logic; output : out std_logic; showstates: out std_logic_vector(3 downto 0) ); end entity; architecture dataflow of rs232_omo is type states is (idle_state,start_state,send_state,stop_state); signal present_state,next_state : states; signal data,data_next : std_logic; begin process(clk,rst) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin if rst='1' then present_state<=idle_state; count:=0; data<='1'; elsif rising_edge(clk) then present_state<=next_state; count:=count+1; index:=index+1; data<=data_next; end if; end process; process(present_state,data,clk,rst,start) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin done<='0'; data_next<='1'; case present_state is when idle_state => showstates<="1000"; data_next<='1'; if start='1' and rst='0' then count:=count+1; if count=clk_max then next_state<=start_state; count:=0; end if; end if; when start_state => showstates<="0100"; data_next<='0'; count:=count+1; if count=clk_max then next_state<=send_state; count:=0; end if; when send_state => showstates<="0010"; count:=count+1; data_next<=input(index); if count=clk_max then if index=7 then index:=0; next_state<=stop_state; else index:=index+1; end if; count:=0; end if; when stop_state => showstates<="0001"; count:=count+1; if count=clk_max then next_state<=idle_state; done<='1'; count:=0; end if; end case; end process; output<=data; end architecture; Constraints: set_property PACKAGE_PIN V17 [get_ports {input[0]}] set_property PACKAGE_PIN V16 [get_ports {input[1]}] set_property PACKAGE_PIN W16 [get_ports {input[2]}] set_property PACKAGE_PIN W17 [get_ports {input[3]}] set_property PACKAGE_PIN W15 [get_ports {input[4]}] set_property PACKAGE_PIN V15 [get_ports {input[5]}] set_property PACKAGE_PIN V14 [get_ports {input[6]}] set_property PACKAGE_PIN W13 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[0]}] set_property PACKAGE_PIN L1 [get_ports {showstates[3]}] set_property PACKAGE_PIN P1 [get_ports {showstates[2]}] set_property PACKAGE_PIN N3 [get_ports {showstates[1]}] set_property PACKAGE_PIN P3 [get_ports {showstates[0]}] set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN R2 [get_ports rst] set_property PACKAGE_PIN T1 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports done] set_property IOSTANDARD LVCMOS33 [get_ports output] set_property PACKAGE_PIN V3 [get_ports done] set_property PACKAGE_PIN V13 [get_ports output] My testbench simulation got attached. And on-board, apparently I stuck with 'idle_state'. For any kind of help, I thank y'all in advance.
  12. How do I implement an external differential clock in VHDL for the CMOD S7? Vivado keeps on telling me to inset this flag in my constraint file: set_property CLOCK_DEDICATED_ROUTE FALSE However, I care about timing because it's an external clock signal. I'm using a clock dedicated route(Pmod pin are 2×6) as seen in this schematic.
  13. Hello everyone. Recently I bought the Pmod i2s2: stereo Audio Input and Output module. I got this working with the example project. As part of the exercise I even translated the I2S part from Verilog to VHDL, and it’s working great by tying the output AXIS directly to the input (without the volume control part). digilent pmod i2s2 code My own vhdl equivalent What I’m a bit confused about, and this may be my limited knowledge of FPGA’s, is that everything is handled on the rising edge of the clock. For example in the digilent pmod i2s2 code in line 135 and 136 the rx_data_l and r register are written on the posedge of the axis_clk. So eventually you get the waveform as in the picture. So far I understand this principle clearly. What I don’t get is why this data on the receive side of the axi is read in on the posedge of the axis_clk. In line 83 and 85 the input data of the axis is written to tx_data_r and l. How can this happen correctly, doesn’t the data bus need some time to change the values. Now it seems that the data is written and read at exactly the same time. Now I want to extend this project by writing the samples into blockram and have the same issue. Can you write the address and data on the same clock as the blockram writes the data, or is it better to write the data on the falling edge for example.
  14. Hello, I have a PmodOLED connected to Nexys 3 board and so far I was able to display ASCII characters by using either the VHDL example code provided by Digilent or the code from Mr. Y.Borrnat from here. I would like to display bitmap graphics. Could you guide me a little? Is it possible to do that by altering one of the codes mentioned? PS: I found a video unfortunatelly without any comments, so I mean something like that or draw a chart perhaps. Thank you.
  15. Hello, I am trying to send a character to FPGA from PC hyper terminal , for eg : 's' to start other processes in FPGA like initiating generation of CCD signals and sampling ADC et al and a different ascii character to stop the processes. I am able to send a ASCII character from PC hyper terminal and receive binary value it on FPGA LED's however I'm unable to use this for control. Please find my top level code below. 'Start' signal is to be controlling the initiation of other processes. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; use IEEE.MATH_REAL.ALL; ----------------------------------------------------- entity top_module is port( --------------------UART_GUI------------------------------- RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); ---COMMON INPUTS--- clk, rst : in std_logic; --send_ccd : in std_logic;---------------CCD control SH,ICG,master_ccd_clock : out std_logic; ----FOR AD7980-------- --sample: in std_logic; -------------- to start sampling samp_ind: out std_logic;---------------indicates sampling in process adc_cnv : out std_logic;---------------cnv for AD7980 adc_clk : inout std_logic;--------------SPI clock adc_miso : in std_logic;------------------output from AD7980 -------FIFO SIGNALS-------- WriteEn , ReadEn : in std_logic; -------------fifo controls full, empty : out std_logic ------------------indicates fifo status ); end top_module; architecture structural of top_module is ----------------------------------------------------------------------------UART CONTROL GUI------------------------------------- component receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END component receiver; ----------------------------------------FIFO COMPONENT DECLARATION ----------------------------------------------------------------- component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; -------------------------------------------------------------------------------------------------------------------------- signal fifo_data_out : STD_LOGIC_VECTOR (15 downto 0); signal adc_out : std_logic_vector(15 downto 0); signal start :std_logic; -------------------------UART_RX_FOR CONTROL_ OF_PROCESSES--------------------------------------------------------------- process(Clk,RxData) begin if RxData = "01110011" then start <= '1' ; elsif RxData = "01110000" then start <= '0'; else start <= '0'; end if; end process; --------------------AD7980PORTMAP---------------------------------------------------------------------------------- AD7980 : entity work.AD7980 port map ( clock => clk, sample => start, -- data output Dout => adc_out(15 downto 0), samp_ind => samp_ind, -- ADC connection adc_miso => adc_miso, adc_cnv => adc_cnv, adc_clk =>adc_clk ); ---------------------------------------------FIFO PORTMAP---------------------------------------------------------------- fifo_i: component fifo port map ( clk_100MHz => clk, din_0(15 downto 0) => adc_out(15 downto 0), dout_0(15 downto 0) => fifo_data_out(15 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); ccd_control : entity work.TCD1103GFG port map ( clock => clk, send => start, SH => SH, ICG => ICG, master_ccd_clock => master_ccd_clock); ---------------------------------------------------------------UART GUI CONTROL--------------------------------------- uart_gui : entity work.receiver port map ( clk => clk, reset => rst, RxD => RxD, RxData => RxData ); end structural; Here is the UART receiver open source code I'm using that works LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END receiver; ARCHITECTURE behavioural OF receiver IS SIGNAL shift : STD_LOGIC; SIGNAL state : STD_LOGIC; SIGNAL nextstate : STD_LOGIC; SIGNAL bitcounter : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL samplecounter : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL counter : STD_LOGIC_VECTOR(13 DOWNTO 0); SIGNAL rxshiftreg : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL clear_bitcounter : STD_LOGIC; SIGNAL inc_bitcounter : STD_LOGIC; SIGNAL inc_samplecounter : STD_LOGIC; SIGNAL clear_samplecounter : STD_LOGIC; constant clk_freq: integer := 100000000; constant baud_rate :integer := 9600; constant div_sample :integer := 4; constant div_counter :integer := (clk_freq/(baud_rate*div_sample)); constant mid_sample : integer := (div_sample/2); constant div_bit : integer := 10; BEGIN RxData <= rxshiftreg(8 DOWNTO 1); PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN state <= '0'; bitcounter <= "0000"; counter <= "00000000000000"; samplecounter <= "00"; ELSE counter <= counter + "00000000000001"; if (counter>= div_counter - 1) then counter <= "00000000000000"; state <= nextstate; IF (shift = '1') THEN rxshiftreg <= (RxD & rxshiftreg(9 DOWNTO 1)); END IF; IF (clear_samplecounter = '1') THEN samplecounter <= "00"; END IF; IF (inc_samplecounter = '1') THEN samplecounter <= samplecounter + "01"; END IF; IF (clear_bitcounter = '1') THEN bitcounter <= "0000"; END IF; IF (inc_bitcounter = '1') THEN bitcounter <= bitcounter + "0001"; END IF; END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN shift <= '0'; clear_samplecounter <= '0'; inc_samplecounter <= '0'; clear_bitcounter <= '0'; inc_bitcounter <= '0'; nextstate <= '0'; CASE state IS WHEN '0' => IF (RxD = '1') THEN nextstate <= '0'; ELSE nextstate <= '1'; clear_bitcounter <= '1'; clear_samplecounter <= '1'; END IF; WHEN '1' => nextstate <= '1'; IF (samplecounter = (mid_sample - 1)) THEN shift <= '1'; END IF; IF (samplecounter = (div_sample - 1)) THEN IF (bitcounter = (div_bit - 1)) THEN nextstate <= '0'; END IF; inc_bitcounter <= '1'; clear_samplecounter <= '1'; ELSE inc_samplecounter <= '1'; END IF; WHEN OTHERS => nextstate <= '0'; END CASE; END IF; END PROCESS; end behavioural; I'm unsure if the issue is because of the number of clock cycles for which the character 's' exists. Please help me understand the miss here.
  16. Hi, I want to use the DD to test an ASIC which needs quite some complicated digital control. First the ASIC needs to be initialized with several SPI commands. Once the device is configured a test sequence (4 digital control lines) will trigger the ASIC and thereby acquire measurement data. At last this data need to read out. I was wondering, if I could use the patterns which are generated by our (VHDL) simulator as input to the DD. Is there a script which can read the vcd-files and Importes them to WaveForms? As I am quite new to this field, I do not have any expierence with JavaScript or Phyton (but willing to learn )
  17. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf
  18. Junior_jessy


    Hello, I'm trying to make a voice-activated on a nesys4 and i want to use the pmodMic3.To do si, I want to use the SPI protocol but i don't know how. So how can i choose the SPI protocol ? Furthermore, I got some issues when filling in the constraint's file. On the web-site of Diligent, the pin2 is not connected but, the protocol SPI show the opposite. So how to Well connect the in/out of the peripheral to the board in the constraint's file? Thank you in advance for your answer. Junior
  19. I am new in VHDL and have a school project. I am reading 40-bit data from DHT11 humidity sensor. Although first 8 bit is meaningful to me, I read all 40. At the end of the transaction, it is required to light 8 LEDs corresponding to each bit of 8bit. I can light the confirmation LED which lights when all 40-bit data is received. But, can’t do it for the data LEDs. I need urgent help. Thanks.
  20. I have connected an ov 7670 camera to my Basys 3 board and want to transmit the frame to a PC via the micro-usb port. I have tried UART serial communication, but the bit per second rate is simply not high enough to transmit a full 640 * 480 frame 15/30 times a second. I had the idea of implementing some sort of parallel communication, however I could not find any information or guides. I was wondering if anyone could help me out either with parallel communication, or suggesting a different method of transmitting frames to a PC. Thanks in advance.
  21. Hi, I have started using PMOD BLE recently and I can make a connection in between BLE and PC using a terminal (with Nexys4DDR making a direct connection in between). However, when I write a VHDL code, describing what I made on the terminal one by one, the BLE device stucks at rebooting. For both applications I use the following sequence that is described in "RN4871_user_guide.pdf" page 59 : - Send $$$ - Wait a second - Send SS,40<CR> (this is to select UART Transparent feature only) - Wait a second - Send R,1<CR> - Wait a second - Wait for an ASCII entry but, at "R,1<CR> ", the BLE device turns the blue LED on (which is LD1 on schematic) and it does not shuts it off no matter what. While so, (I mean when the LED is ON) the iOS application SmartDiscover (or anyother terminal) cannot see the module. So, I cannot reach the device at all. Besides, the device returns this when connected via PC terminal (through cable) => CMD> AOK<\r><\n>CMD> Rebooting<\r><\n>%REBOOT% and returns this when FPGA communicates with the device directly => CMD> AOK<\r><\n>CMD> Rebooting<\r><\n> so, it does not return me %REBOOT% string, but seems like it stucks at some point where it is trying to reboot itself. Any help with this would be very nice at this point, Thanks in advance, Bera
  22. Hi, guys, I am in need of a Digilent board to run Linux with a GUI to have access to IOpins and peripherals, and also to work together with the vhdl codes on the FPGA. I am not sure how to install Linux on SD card, start a boot from there, ANDhave at the same time a vhdl code running on FPGA that I could edit and compile using the vivado (2018.2). The idea is to have the vhdl code running the hardware and the GUI on linux to present values of input, output, make the configuration on-line of the vhdl variables, etc... I was thinking about the Zybo board. Can someone give me, please, some directions and/or suggestions? Regards,
  23. macellan

    XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================
  24. This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  25. Hi all, I am doing a project on vhdl in which i am trying to display a pattern (like forming an eight) on seven segment display on spartan 3 fpga kit.I have written the vhdl code and simulation works correctly,but the problem is i am not able to write the ucf code (written but may be wrong) required for implementation on spartan 3 kit.I would highly greatful if anyone can help me as to how to write ucf code or modify my vhdl code. Thanks in advance. Regards, Nikhil Singh pattern generator.txt