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Found 31 results

  1. Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display the image. summary of code functionality: Divide main 100 MHz clock by four to get 25 MHz clock (required pixel frequency) , establish VGA synchronization and display the image on a 640 x 480 resolution @ 60 Hz. The code is shown below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity vga_driver is Port ( clk : in STD_LOGIC; --100 MHz main clock. Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; R,G,B : out STD_LOGIC_VECTOR (3 downto 0)); end vga_driver; architecture Behavioral of vga_driver is signal DFlipFlopOut1: STD_LOGIC; signal DFlipFlopOut1_NOT: STD_LOGIC; signal ClockDiv4: STD_LOGIC; -- 25 MHz Clock signal ClockDiv4_NOT: STD_LOGIC; constant picture_size : Integer:=90000; -- 300 Pixels* 300 Pixels picture= 90000 Pixels --Signals for Block RAM signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0):="0"; signal addra : STD_LOGIC_VECTOR(16 DOWNTO 0):=(others=>'0'); signal dina : STD_LOGIC_VECTOR(11 DOWNTO 0):=(others=>'0'); signal douta : STD_LOGIC_VECTOR(11 DOWNTO 0):=(others=>'0'); constant HD : integer := 639; -- 639 Horizontal Display (640) constant HFP : integer := 16; -- 16 Right border (front porch) constant HSP : integer := 96; -- 96 Sync pulse (Retrace) constant HBP : integer := 48; -- 48 Left boarder (back porch) constant VD : integer := 479; -- 479 Vertical Display (480) constant VFP : integer := 10; -- 10 Right border (front porch) constant VSP : integer := 2; -- 2 Sync pulse (Retrace) constant VBP : integer := 33; -- 33 Left boarder (back porch) signal hPos : integer := 0; signal vPos : integer := 0; signal videoOn : std_logic := '0'; component RisingEdge_DFlipFlop is port( Q : out std_logic; Clk :in std_logic; D :in std_logic ); end component ; component Picture_Block_RAM is PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); end component; begin DFlipFlopOut1_NOT<=not DFlipFlopOut1; ClockDiv4_NOT<= not ClockDiv4; --Pass Main 100 MHz clock to 2 cascaded DFlipFLops to divide frequency by 4. Result frequency= 25 MHz. U1: RisingEdge_DFlipFlop Port map (clk=> clk, D=> DFlipFlopOut1_NOT, Q=>DFlipFlopOut1); U2: RisingEdge_DFlipFlop Port map (clk=> DFlipFlopOut1, D=> ClockDiv4_NOT, Q=>ClockDiv4); --Block RAM containing picture U3: Picture_Block_RAM Port map (clka=>ClockDiv4, wea=>wea, addra=>addra, dina=>dina, douta=>douta); Horizontal_position_counter:process(ClockDiv4) begin if(ClockDiv4'event and ClockDiv4 = '1')then if (hPos = (HD + HFP + HSP + HBP)) then hPos <= 0; else hPos <= hPos + 1; end if; end if; end process; Vertical_position_counter:process(ClockDiv4, hPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(hPos = (HD + HFP + HSP + HBP))then if (vPos = (VD + VFP + VSP + VBP)) then vPos <= 0; else vPos <= vPos + 1; end if; end if; end if; end process; Horizontal_Synchronisation:process(ClockDiv4, hPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if((hPos <= (HD + HFP)) OR (hPos > HD + HFP + HSP))then HSYNC <= '1'; else HSYNC <= '0'; end if; end if; end process; Vertical_Synchronisation:process(ClockDiv4, vPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if((vPos <= (VD + VFP)) OR (vPos > VD + VFP + VSP))then VSYNC <= '1'; else VSYNC <= '0'; end if; end if; end process; video_on:process(ClockDiv4, hPos, vPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(hPos <= HD and vPos <= VD)then videoOn <= '1'; else videoOn <= '0'; end if; end if; end process; draw:process(ClockDiv4, hPos, vPos, videoOn) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(videoOn = '1')then if (unsigned(addra)<picture_size) then R<=douta(11 downto 8); G<=douta(7 downto 4); B<=douta(3 downto 0); addra<=STD_LOGIC_VECTOR(unsigned(addra)+1); else R<=(others=>'0');G<=(others=>'0');B<=(others=>'0'); end if; else R<=(others=>'0');G<=(others=>'0');B<=(others=>'0'); addra<=(others=>'0'); end if; end if; end process; end Behavioral; My problem is that the image does not display as expected. I get this displayed on my screen: As you see, there are 2 problems immediately noticed. 1st: The image is not the same, obviously. 2nd: The image should not take the whole display since it is 300 * 300 pixels while the resolution is 640*480 pixels meaning that some data is being repeated without intention. The default display of BASYS 3 is this. I am putting this just for reference so you can know how my screen displays 640*480 resolution: I tested the VHDL code by printing colors on my screen by direct output assignment and it works as intended. So the problem is probably with accessing the block RAM. A snippet from my .coe file: MEMORY_INITIALIZATION_RADIX=2; MEMORY_INITIALIZATION_VECTOR= 011101010100, 010101110111, 000110011111, 010110101100, 000110111111, 001000100010, 001000100010, 001000100010, 001000100011, 000101100100, 100110100001, 111011010110, 111110110110, 111110000101, 111110010100, : : --it goes on and on until last line, line number 90002, 90000 since 300*300 pixels= 90000. The added two is due to the first 2 lines. : : 101100100010; I am stuck at this point. Where could the problem be?
  2. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as provided in file Regarding error: their is no error or any critical warning is shown in vivado 2016.2 version bur still nothing shows,even though i have provided external power supply 5v to it and change jumper to its specific part edge detetion works fine and show rover output so i imported it in design and the complete design image i add in attachment.( i have twice check the hdmi cable ,vga projector and lp output all works fine) i have attach xdc file and desing image i m using zybo board having specific xc7z010clg400-1 part pls provide some solution or any other help ASAP Zybo_B.xdc
  3. Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 Part 2: Bitmap display using your own image: https://timetoexplore.net/blog/arty-fpga-vga-verilog-02 Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will
  4. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it never gets set high. Does anyone have any idea what I might have setup wrong or if I'm missing something?
  5. Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  6. dgottesm

    Sync on green VGA

    General question: Has anyone here ever managed to do a VGA project with 'sync on green' to drive component video? Looking for the most basic implementation, looking for a stable picture, not quality
  7. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  8. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  9. hi.. ! I need a fpga devolpment board with VGA and HDMI as input and HDMI or DVI or both as output. i googled but not find a single board with these connectors together. Thanks in Advance.
  10. Dear experts, I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? thanks- Shuvo
  11. Dear Experts, The hdmi in to vga out demo project gives perfect resolution at 1080p settings. But, wherever I try to set other resolution as I need 720p, it gives me extended resolution. Is there any option that I can fix it at 720p? Coz the monitor I want to use for output doesn't support Full HD (1080p) resolution. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start Regards- Shuvo
  12. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo
  13. Dear experts, I am actually new in this field and have a very few experience with zybo board. I have implemented the zybo_hdmi_in_demo which is required for my master thesis. Output video streaming at the VGA monitor shows a cropped part of my input video source. What should I do now? And can I use other HDMI source rather than my PC? And what is the preferred input HDMI video resolution? any kind of support or suggestions is highly appreciated.
  14. Hello everyone! I'm not sure whether this forum is the right place to ask this question but still. I have connected a low-cost OV7670 camera to this Digilent example: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start?redirect=1 Here is what I've done. I took the OV7670 - > AXI4Stream core from here (link below) and attached it instead of HDMI input. I changed this module to have not 32 bit RGBA output but 24 bit RGB input https://lauri.xn--vsandi-pxa.com/hdl/zynq/xilinx-video-capture.html and also I took the OV7670 Controller from here (link below) and also attached it to the design https://lauri.xn--vsandi-pxa.com/hdl/zynq/zybo-ov7670-to-vga.html The system works o'k. What I would like to do is to remove the HDMI part from this design. I just want the image to be captured by the camera and be shown on VGA screen. If I understand it right the axi_gpio_video and the v_tc_1 ip-cores send some interrupt essential for the stream to start. I am interested and I have no understanding of what I have to do to remove the HDMI part from the design so that I always saw the image from my OV7670. Do I have to somehow simulate the interrupts? Can I do this in C code? Thank you very much for response in advance.
  15. I'm making a project about image processing. The board used in the project is the Zybo board and operates on a frame 1920x1080 (Full HD). My project is Square Area Detection Then motion detection within the rectangular area. I would like to ask for advice or guidance directs the operation of the mine. (I'm new to Zybo boards and I just learned recently.) If anyone has suggestions and links for learning. Please direct me and attach the link. Thanks in advance. ^__^
  16. Hi Everyone, I was trying to capturing hdmi signal and display video on VGA monitor using DVI to RGB IP Core (version 1.6 or 1.7). Everything works correctly for 800x600 1024x768 and 1280x720. But for other resolutions (1280x1024 1600x900 1680x1050 and 1920x1080) image on external VGA monitor has very poor quality. Could anyone suggest where is the problem. In dvi2rgb spec I've found info about constraining tmds clock so based on my calculation for ZYBO IP Core should work correctly for 1680x1050 resoultion (tmds clock is about 120). I am using this IP Core in bigger project and I need to explain where is the problem. I can also upload my project in Vivado. Thanks for any help
  17. Hi, I am trying to develop a simple project for HDMI to RGB. I am using dvi2rgb core and clock_wizard for generating a reference clock for it. I supplied 200MHz to dvi2rgb. I tried both MMCM and PLL modes in clock_wizard configuration. But when I dump the bitstream on Zybo Vivado shows the following warnings and my design doesn't work. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution:1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. Attached are my block diagram which I'm implementing, and my constraints file. Please help me. I have read a lot of posts on this project but couldn't find any solution that can work for me. If you want my project file I can attach it as well. Thanks ZYBO_Master.xdc
  18. s224071

    VGA on Zybo

    Hello, First of all, I'm a beginner. I'd like to use my zybo board to print a simple image on a screen using the VGA port. I looked for some tutorials, but either they are all working on older version of Vivado (mine is 2016.4), therefore the vhdl file have compatibility problems, or they are not so clear about how to actually configure the board to use the VGA. I really just want to do something simple, like printing a static ball on the screen... Can somebody help me to understand how to do this? Gianluca
  19. Hello everyone, I just started learning VHDL and digital design on my college and as a term project I am to design a digital circuit which will output a game through VGA pins. I first started examining examples on the internet and tried to synthetise myself on Vivado Design Suite. However, I encountered problems. The following is the code which I use to synchronize image. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sync_module is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; start : in STD_LOGIC; y_control : out STD_LOGIC_VECTOR (9 downto 0); x_control : out STD_LOGIC_VECTOR (9 downto 0); h_s : out STD_LOGIC; v_s : out STD_LOGIC; video_on : out STD_LOGIC); end sync_module; architecture Behavioral of sync_module is -- Video Parameters constant HR:integer:=1280;--Horizontal Resolution constant HFP:integer:=48;--Horizontal Front Porch constant HBP:integer:=248;--Horizontal Back Porch constant HRet:integer:=112;--Horizontal retrace constant VR:integer:=1024;--Vertical Resolution constant VFP:integer:=1;--Vertical Front Porch constant VBP:integer:=38;--Vertical Back Porch constant VRet:integer:=3;--Vertical Retrace --sync counter signal counter_h,counter_h_next: integer range 0 to 799; signal counter_v,counter_v_next: integer range 0 to 524; --mod 2 counter signal counter_mod2,counter_mod2_next: std_logic:='0'; --State signals signal h_end, v_end:std_logic:='0'; --Output Signals(buffer) signal hs_buffer,hs_buffer_next:std_logic:='0'; signal vs_buffer,vs_buffer_next:std_logic:='0'; --pixel counter signal x_counter, x_counter_next:integer range 0 to 900; signal y_counter, y_counter_next:integer range 0 to 900; --video_on_off signal video:std_logic; begin --clk register process(clk,reset,start) begin if reset ='1' then counter_h<=0; counter_v<=0; hs_buffer<='0'; hs_buffer<='0'; counter_mod2<='0'; elsif clk'event and clk='1' then if start='1' then counter_h<=counter_h_next; counter_v<=counter_v_next; x_counter<=x_counter_next; y_counter<=y_counter_next; hs_buffer<=hs_buffer_next; vs_buffer<=vs_buffer_next; counter_mod2<=counter_mod2_next; end if; end if; end process; --video on/off video <= '1' when (counter_v >= VBP) and (counter_v < VBP + VR) and (counter_h >=HBP) and (counter_h < HBP + HR) else '0'; --mod 2 counter counter_mod2_next<=not counter_mod2; --end of Horizontal scanning h_end<= '1' when counter_h=799 else '0'; -- end of Vertical scanning v_end<= '1' when counter_v=524 else '0'; -- Horizontal Counter process(counter_h,counter_mod2,h_end) begin counter_h_next<=counter_h; if counter_mod2= '1' then if h_end='1' then counter_h_next<=0; else counter_h_next<=counter_h+1; end if; end if; end process; -- Vertical Counter process(counter_v,counter_mod2,h_end,v_end) begin counter_v_next <= counter_v; if counter_mod2= '1' and h_end='1' then if v_end='1' then counter_v_next<=0; else counter_v_next<=counter_v+1; end if; end if; end process; --pixel x counter process(x_counter,counter_mod2,h_end,video) begin x_counter_next<=x_counter; if video = '1' then if counter_mod2= '1' then if x_counter= 639 then x_counter_next<=0; else x_counter_next<=x_counter + 1; end if; end if; else x_counter_next<=0; end if; end process; --pixel y counter process(y_counter,counter_mod2,h_end,counter_v) begin y_counter_next<=y_counter; if counter_mod2= '1' and h_end='1' then if counter_v >32 and counter_v <512 then y_counter_next<=y_counter + 1; else y_counter_next<=0; end if; end if; end process; --buffer hs_buffer_next<= '1' when counter_h < 704 else--(HBP+HGO+HFP) '0'; vs_buffer_next<='1' when counter_v < 523 else--(VBP+VGO+VFP) '0'; --outputs y_control <= conv_std_logic_vector(y_counter,10); x_control <= conv_std_logic_vector(x_counter,10); h_s<= hs_buffer; v_s<= vs_buffer; video_on<=video; end Behavioral; ...and the following is a snippet from my constraints file : set_property PACKAGE_PIN N19 [get_ports {rgb[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] set_property PACKAGE_PIN J18 [get_ports {rgb[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] set_property PACKAGE_PIN D17 [get_ports {rgb[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] set_property PACKAGE_PIN P19 [get_ports h_s] set_property IOSTANDARD LVCMOS33 [get_ports h_s] set_property PACKAGE_PIN R19 [get_ports v_s] set_property IOSTANDARD LVCMOS33 [get_ports v_s] ## END VGA CONNECTOR I went through google results for this "out of range" problem and none of them solved my problem. Then I connected my oscilloscope to the output of the horizontal sync and vertical sync. This is from the 13 pin of the VGA output : And this is the output of the 14. pin: So what do you think my problem is? The default demo on BASYS3 runs flawlessly.
  20. Hi all, I am a new user of basys3 board and I need your help about the "Built in Self Test " of this link https://reference.digilentinc.com/basys3/refmanual Can you share me the source code of this self test and the IP cores used to this self test. Regards,
  21. I am attempting to sample values from the XADC and use those values to control a video display connected via VGA. Both of these parts work separately, but when I attempt to combine the hardware for the two, the XADC stops working. Specifically, the XADC still returns values, and those values still fluctuate slightly, but they don't represent the voltage anymore. I'm using the XADC in single channel mode, and have tried both channels 6 and 14. I've connected my analog input to PMOD-JA in the appropriate places for channel 6 and 14. Both of these channels function perfectly in my XADC only design, but when I add the VGA display hardware they stop working. The values returned by the XADC still fluctuate, so it's sampling something, just not the thing I want it to sample. For example, I had a voltage difference of approximately 0.37 volts across channel 14 and some of the 16-bit values returned by the XADC were 206, 187, 196, 226, 201, 220, 201, 187, 222, 229, 192, 213, and 225. These values stay in this 100-200 range even if the voltage is changed. Again, the correct values are returned when using the hardware without the VGA display. Adding the VGA hardware breaks it. I'm interested to know if anyone has successfully used both the VGA output and the XADC in the same project, and if they had to do anything special to get the setup working. If necessary, I could provide code or a Vivado project that demonstrates my issue. Thanks!
  22. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,
  23. I've got a HDMI link set up between two Zybos using Digilent's DVI cores (rgb2dvi and dvi2rgb). Having tested everything successfully using a 1080p pipeline, however upon switching to VGA resolutions (640x480) the sink part cannot successfully decode the stream. It never occurred to me that low resolutions would pose an issue - but I've been banging my head on a wall with this one! As per the documentation, I've adjusted some constraints and multiplier / divider combinations for the MMCM in the dvi2rgb core and the clock recovery block is successfully recovering my 25.175 MHz pixel clock (although interestingly it is somehow still able to recover it when the MMCM is configured for 1080p - something I wasn't expecting as the VCO is operating way out of spec at 125 MHz). I'm not getting any activity on the pVDE or CTRL signals, so I think there's something up with the phase alignment or channel bonding. Receiver block diagram is attached, but it's pretty standard. Any clues? EDIT: I've just noticed that the documentation lists the lower limit for the pixel clock as 40 MHz. Initially I thought this was due to the VCO range, but I also just noticed that the 32-tap delay spans 2.5ns, which happens to be the period of a single bit at 40 Hz. Is my limitation down to the deskew implementation?
  24. Hello! My task is creation of real-time system which can draw simple graphics figure on monitor (VGA) when the system register input pulse. The main difficulty is to draw this image only once (for measuring man's reaction time: time between image drawing and the button pressing). I think it'll possible to use FPGA to register input pulse and to generate VGA signal with required parameters. But I don't undestand can the ONLY ONE image frame be drawn at input pulse interrupting or not? The main task is to minimize time delays and in this case I can't use the standart solutions. For example, using Raspberry Pi or a similar device is accompanied by the necessary of screen refreshing and image drawing binding. This adds a random time delay from 0ms (if the screen refresh time coincides with time of input external pulse which starts drawing figures) to 1/60Hz=16.7ms. I need your advices or suggestions. Thanks!
  25. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ