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  1. Hi, I want to develop a simple subsystem that is shown on the picture below. Basically, I need one producer that would generate a picture(s) and one consumer that would display the picture. The consumer is easier part, it's VGA block that reads the pictures from the memory. I want to use a bigger resolution, so I cannot use BRAM and I have to go for DDR. I'm planning to use MIG for this job. The question is whether I can configure DDR as a dual-port ram (one port for generator and one port for consumer). Is it possible? If not, I think that I have to go with multi-master bus, so the consu
  2. Hello, I try to generate a VGA signal with a VDMA, Video Timing, and AXI4 Stream to Video Out IP for my Zybo. So I create the following block design with the given settings (Note: I test the design with the test pattern generator instead of the VDMA before, so I know that the settings of the Timing Generator and Video Out IP are correct). My code looks like this: #ifdef WITH_TESTPATTERN #include "xv_tpg.h" #endif #include "xaxivdma.h" #include "xparameters.h" #ifdef WITH_TESTPATTERN XV_tpg TPG; XV_tpg_Config* TPG_Config; #endif XAxiVdma_Config* VDMA_Config; XAxiVdma VDMA; X
  3. s224071

    VGA on Zybo

    Hello, First of all, I'm a beginner. I'd like to use my zybo board to print a simple image on a screen using the VGA port. I looked for some tutorials, but either they are all working on older version of Vivado (mine is 2016.4), therefore the vhdl file have compatibility problems, or they are not so clear about how to actually configure the board to use the VGA. I really just want to do something simple, like printing a static ball on the screen... Can somebody help me to understand how to do this? Gianluca
  4. Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display
  5. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as
  6. Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 Part 2: Bitmap display using your own image: https://timetoexplore.net/blog/arty-fpga-vga-verilog-02 Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will
  7. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it nev
  8. Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  9. dgottesm

    Sync on green VGA

    General question: Has anyone here ever managed to do a VGA project with 'sync on green' to drive component video? Looking for the most basic implementation, looking for a stable picture, not quality
  10. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats th
  11. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats th
  12. hi.. ! I need a fpga devolpment board with VGA and HDMI as input and HDMI or DVI or both as output. i googled but not find a single board with these connectors together. Thanks in Advance.
  13. Dear experts, I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? thanks- Shuvo
  14. Dear Experts, The hdmi in to vga out demo project gives perfect resolution at 1080p settings. But, wherever I try to set other resolution as I need 720p, it gives me extended resolution. Is there any option that I can fix it at 720p? Coz the monitor I want to use for output doesn't support Full HD (1080p) resolution. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start Regards- Shuvo
  15. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negati
  16. Dear experts, I am actually new in this field and have a very few experience with zybo board. I have implemented the zybo_hdmi_in_demo which is required for my master thesis. Output video streaming at the VGA monitor shows a cropped part of my input video source. What should I do now? And can I use other HDMI source rather than my PC? And what is the preferred input HDMI video resolution? any kind of support or suggestions is highly appreciated.
  17. Hello everyone! I'm not sure whether this forum is the right place to ask this question but still. I have connected a low-cost OV7670 camera to this Digilent example: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start?redirect=1 Here is what I've done. I took the OV7670 - > AXI4Stream core from here (link below) and attached it instead of HDMI input. I changed this module to have not 32 bit RGBA output but 24 bit RGB input https://lauri.xn--vsandi-pxa.com/hdl/zynq/xilinx-video-capture.html and also I took the OV7670 Contro
  18. I'm making a project about image processing. The board used in the project is the Zybo board and operates on a frame 1920x1080 (Full HD). My project is Square Area Detection Then motion detection within the rectangular area. I would like to ask for advice or guidance directs the operation of the mine. (I'm new to Zybo boards and I just learned recently.) If anyone has suggestions and links for learning. Please direct me and attach the link. Thanks in advance. ^__^
  19. Hi Everyone, I was trying to capturing hdmi signal and display video on VGA monitor using DVI to RGB IP Core (version 1.6 or 1.7). Everything works correctly for 800x600 1024x768 and 1280x720. But for other resolutions (1280x1024 1600x900 1680x1050 and 1920x1080) image on external VGA monitor has very poor quality. Could anyone suggest where is the problem. In dvi2rgb spec I've found info about constraining tmds clock so based on my calculation for ZYBO IP Core should work correctly for 1680x1050 resoultion (tmds clock is about 120). I am using this IP Core in bigger project and I need to
  20. Hi, I am trying to develop a simple project for HDMI to RGB. I am using dvi2rgb core and clock_wizard for generating a reference clock for it. I supplied 200MHz to dvi2rgb. I tried both MMCM and PLL modes in clock_wizard configuration. But when I dump the bitstream on Zybo Vivado shows the following warnings and my design doesn't work. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution:1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR2. Manually launch hw_server with -e "se
  21. Hello everyone, I just started learning VHDL and digital design on my college and as a term project I am to design a digital circuit which will output a game through VGA pins. I first started examining examples on the internet and tried to synthetise myself on Vivado Design Suite. However, I encountered problems. The following is the code which I use to synchronize image. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sync_module is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; sta
  22. Hi all, I am a new user of basys3 board and I need your help about the "Built in Self Test " of this link https://reference.digilentinc.com/basys3/refmanual Can you share me the source code of this self test and the IP cores used to this self test. Regards,
  23. I am attempting to sample values from the XADC and use those values to control a video display connected via VGA. Both of these parts work separately, but when I attempt to combine the hardware for the two, the XADC stops working. Specifically, the XADC still returns values, and those values still fluctuate slightly, but they don't represent the voltage anymore. I'm using the XADC in single channel mode, and have tried both channels 6 and 14. I've connected my analog input to PMOD-JA in the appropriate places for channel 6 and 14. Both of these channels function perfectly in my XADC o
  24. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,
  25. I've got a HDMI link set up between two Zybos using Digilent's DVI cores (rgb2dvi and dvi2rgb). Having tested everything successfully using a 1080p pipeline, however upon switching to VGA resolutions (640x480) the sink part cannot successfully decode the stream. It never occurred to me that low resolutions would pose an issue - but I've been banging my head on a wall with this one! As per the documentation, I've adjusted some constraints and multiplier / divider combinations for the MMCM in the dvi2rgb core and the clock recovery block is successfully recovering my 25.175 MHz pixel clock