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Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth), as well as test benches for i2s_tx and Basys3_Abacus_top. All of these files are relatively simple. In addition, I've attached the constraint file, and an image of the output, taken with my DSO NANO V3. Furthermore, I've zipped up the entire project and uploaded here: https://drive.google.com/file/d/0B_8d0gTEx0yqaDFyOUhCTGU0QW8/view?usp=sharing Some thoughts: Maybe SSM2518 doesn't know to generate MCLK as 4xBCLK? Faulty chip? Anyways, if one of you has the time and energy to either point out flaws in my verilog or hardware setup, I would be very grateful. TIA oscillator.v i2s_tx.v sclk_div.v i2stx_tb.v Basys3_Master.xdc Basys3_Abacus_Top.v IMG_001.BMP