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Found 55 results

  1. Hi! I want to read the output data of a delta-sigma modulation based ADC (AD7402) using NI LabVIEW FPGA. Can you help me by explaining what the Verilog code in the attached datasheet (page 17) does? AD7402.pdf
  2. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for the negative edge data. My next step which Im currently working on is to insert this data into the FFT IP module which Lattice provides. ( I attached timing digrams (timings.pdf). The FFT IP Im creating is 12bit width input/output so I need to time the input flags in a way that it take first data from the positive edge FIFO and the next data from the negative edge FIFO and processing so on in a stream. Of course Im paying attention to all the flags as the IP telling. I want to ask some guidelines questions about how to do it correctly. 1. Do I need a state machine which indicates when the FIFO is full and only then to read the data into the FFT input? Or I can start writing to the FFT without state machine and just counter register which indicate when is read enable asserted and start reading to the FFT? 2. Do I need to fill the FIFO and then read the data until its empty, or I can write to the FIFO and read from the FIFO to the FFT continuously? 3. Any guideline how to make this task correctly? I never did this before.. From my prepective I would just wait for ready flag from the FFT IP and read_enable from the FIFO and start to provide data to the FFT IP but I told the there is more timing managment to be made. thanks. timings.pdf
  3. i enter 5V in FFT so maybe the result are just on impulse signal. but actuality my result have unexpected -'128 signals' (263~390 cnt ) why does -128 apear. and how to disapear unexpected value (-128)
  4. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle. Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing?? Looking forward to you suggestions and other similar references. Thanks in advance
  5. Ahmed Alfadhel


    Hi , I want to learn Verilog . What you suggest for me to start with ? Any recommended books , websites or online courses? Thanks
  6. Ahmed Alfadhel

    Verilog Simulator

    Hi @[email protected] Thanks for your replies to my questions . They are very helpful . I just want to know does it possible to download Verilator on Windows? If not possible , what are the available options for me to download a Verilog Simulator on Windows? Thanks.
  7. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  8. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. Is the connection is ok? What will be other connections needed?
  9. I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation. I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity? EDIT: Verilog module(originally a testbench for another project): module testoverlay_0( input wire rst_n, input wire clk, output reg[23:0] RGBOut, output reg HSync1, output reg VSync1 ); VHDL: component testoverlay_0 is port ( rst_n: in STD_LOGIC; clk: in STD_LOGIC; RGBOut: out STD_LOGIC_VECTOR ( 23 downto 0 ); HSync1: out STD_LOGIC; VSync1: out STD_LOGIC ); end component testoverlay_0; test_overlay: component testoverlay_0 port map ( rst_n => reset_1, clk => sys_clk_i_1, RGBOut(23 downto 0) => v_axi4s_vid_out_0_vid_io_out_DATA_1(23 downto 0), HSync1 => v_axi4s_vid_out_0_vid_io_out_HSYNC_1, VSync1 => v_axi4s_vid_out_0_vid_io_out_VSYNC_1 );
  10. I'm a sophomore student and new to FPGA. I want to use two Basys2 boards and two pmodrf1 modules to transport messages. I looked for some examples on Internet but failed to find an available code. Could anyone please give me a complete verilog code about this? Now I am only able to create .v files to accomplish my work. If your solution is not in this way, I expect you to show me what to do step by step. Thank you!
  11. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am using the Vivado IP Catalog for generating the clock signal and the 4 binary counters(2) used on each 7-Segiment display digit. The Verilog code and constraint file are attached. The binary counter configuration: Implementing using: Fabric Output width: 4 [3:0] Increment Value (Hex): 1 Restrict Count (Hex): 4, 5, 9, 9 (7seg from left ro right) Count Mode: UP Clock Enable (CE): Checked Synchronous Clear(SCLR): Checked Init Value:(Hex): 0 Synchronous Controls and Clock Enable(CE) Priority: Sync Overrides CE Latency Configuration: Manual, 1 Feedback Latency Configuration: Manual, 0 I suspect I am overseeing/forgetting somewhere a simple detail. Any help/clarification is appreciated. Cheers, Rafael. (1) (2) lab9_3_1.v Basys-3-Master.xdc
  12. Hi All: I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get. The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems. The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0]. 1. I added in the additional input - input [1:0] sw 2. I added in the case statement (which is currently commented out) 3. I commented out the original assignment of led - //assign led = clkdiv[26]; The problem crops up immediately with a Verilog error showing on the following line: case(sw) - The error states: Error: 'sw' is not a constant I've spent hours trying various changes...all to no avail. HELP....PLEASE!!!! Thanks Tons! VERILOG MODULE: module clk_divider( input clk, input rst, input [1:0] sw, output led ); wire [26:0] din; wire [26:0] clkdiv; dff dff_inst ( .clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]) ); genvar i; generate for (i = 1; i < 27; i=i+1) begin : dff_gen_label dff dff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din), .Q(clkdiv) ); end endgenerate assign din = ~clkdiv; /* begin case(sw) 2'b00: assign led = clkdiv[26]; 2'b01: assign led = clkdiv[25]; 2'b10: assign led = clkdiv[24]; 2'b11: assign led = clkdiv[23]; default: assign led = clkdiv[26]; endcase end */ assign led = clkdiv[26]; endmodule
  13. Hello everyone. Recently I bought the Pmod i2s2: stereo Audio Input and Output module. I got this working with the example project. As part of the exercise I even translated the I2S part from Verilog to VHDL, and it’s working great by tying the output AXIS directly to the input (without the volume control part). digilent pmod i2s2 code My own vhdl equivalent What I’m a bit confused about, and this may be my limited knowledge of FPGA’s, is that everything is handled on the rising edge of the clock. For example in the digilent pmod i2s2 code in line 135 and 136 the rx_data_l and r register are written on the posedge of the axis_clk. So eventually you get the waveform as in the picture. So far I understand this principle clearly. What I don’t get is why this data on the receive side of the axi is read in on the posedge of the axis_clk. In line 83 and 85 the input data of the axis is written to tx_data_r and l. How can this happen correctly, doesn’t the data bus need some time to change the values. Now it seems that the data is written and read at exactly the same time. Now I want to extend this project by writing the samples into blockram and have the same issue. Can you write the address and data on the same clock as the blockram writes the data, or is it better to write the data on the falling edge for example.
  14. NiLo

    Nexys 3 Pmod Nav Problem

    Hi, I am doing a project on Nexys 3 FPGA board and I am trying to connect Pmod Nav in order to display barometric pressure on PmodOLEDrgb. I am in trouble with Pmod Nav. I have created a Controller that reads via SPI Protocol the 24 bits of 3 data registers and then I have divided this result with value 4097 counts/hPa as it is mentioned in LPS25HB, in order to take the absolute pressure in hPa. The final value should be in range of 260- 1260 hPa. The problem is that the final absolute value of barometric pressure, that I take, is 4095, which means that all bits are stored in 3 registers PRESS_OUT_H, PRESS_OUT_L and PRESS_OUT_XL take the value of '1'. The pins that I have connected are SDI, SDO, SPC, CS_ALT. I have no idea on how to deal with this problem. I would appreciate if someone helped me. Thank you Nik
  15. Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable . Best, ATIF JAVED
  16. I've coded UART receiver and transmitter separately in verilog and tested them on Basys 3 FPGA board with Tera Term terminal. I want to connect a USB Keyboard with the board and on pressing keys on keyboard, they gets reflected on Tera Term at same time. ToDo: Basys 3 Board receives data from keyboard and then transmits that data to elsewhere (say Tera Term terminal or a Pmod LCD screen) Problem:- Can anyone help me in how to use USB Keyboard with Basys 3 and how can I implement my UART in this. Attechments: UART receiver and transmitter code is attached below. UART_tx.v UART_Rx.v
  17. Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs and outputs and see how the timing diagram behaves and try to implement the logic based off of that? Or should I be first be treating this as a "state machine" and draw a systematic schematic of showing all the inputs and outputs, showing when they should go HIGH or LOW at their certain times? Are timing diagrams usually implemented in a state machine logical flow? Was hoping to gain some knowledge and understanding from the people who are experienced writing Verilog logic based off of timing diagrams and was hoping to see your systematic approach of how it should be implemented as if I was an engineer. Thank You.
  18. I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet: module coedata(clk,rst,a); input clk,rst; output [31:0]a; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out); // just gives count in 'out' to access address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule This is ok. I can read value through instantiating once a clock. But I want to store all these values into 2D wire such as [31:0] a[0:100].I want all the values to be available in one clock pulse.(Just assume we have created a sufficient ROM block) module coedata(clk,rst); input clk,rst; reg [31:0]a[0:99]; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out,i); // just gives count in 'out-binary' to access,'i-integer' address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule It is saying that 'i' is not a constant. Thanks in advance.
  19. can we use output from python code in verilog on pynq board. e.g if we take hdmi in python. Can we process that frames in verilog.? Thanks
  20. elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator is not taking any inputs according to the module. thanks elevator12.txt
  21. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  22. I have a PmodOLED display board connected to the JA header on an ARTY board by Digilent. I am using Verilog and have tried version 16.4 and 17.1. I am using the supplied sample code to write to the display for the first time. When I try to "Program Device" I get the following error message: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. Can someone please tell me what the problem may be? Thanks, Dave
  23. tekson


    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  24. I am trying to implement Decimation on FPGA and Matlab For this task i chose following design parameters Filter type=window hamming hamming method filter order=30 decimation factor=10 input sample rate=2Ms/s output sample rate=200ks/s Normalized cuttof =1/decimation factor First i implement it on MATLAB and use this sequence Filter handle filter delay downsample Using above sequence i successfuly implement it on MATLAB For FPGA i use fir compiler core in which i paste the same coefficients that is generated through matlab But the problem i face is fir compiler core directly gives you the decimated output without handling fitler delay so what should i do if want to handle this filter delay in xilinx Fir compiler core sequence Filter-downsample
  25. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz