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Hello fellow makers, I am trying to get some grasp of CPU RTL and toolchain design and ZipCPU showed up in my search result and looks very promising. However the verilog coding style really confuses me. I use ncsim 2015 for my office work and used Verilog for at least ten years. Now I tried to simulate the ZipCPU core RTL but it had too many syntax errors. The most obvious one being variables being used before it's declared, e.g. r_wb_cyc_gbl. Here comes my question, is the bugs I saw as a result of I use ncsim or difference between ncsim and verilator? Anybody run simulation with Vivado simulator? Another question, where is the best website, material or lectures to study how to customize GCC for my custom instruction set? Thank you!