Search the Community

Showing results for tags 'verilog zipcpu ×'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. imc_user1

    Verilog coding format used by ZipCPU.

    Hello fellow makers, I am trying to get some grasp of CPU RTL and toolchain design and ZipCPU showed up in my search result and looks very promising. However the verilog coding style really confuses me. I use ncsim 2015 for my office work and used Verilog for at least ten years. Now I tried to simulate the ZipCPU core RTL but it had too many syntax errors. The most obvious one being variables being used before it's declared, e.g. r_wb_cyc_gbl. Here comes my question, is the bugs I saw as a result of I use ncsim or difference between ncsim and verilator? Anybody run simulation with Vivado simulator? Another question, where is the best website, material or lectures to study how to customize GCC for my custom instruction set? Thank you!
  2. Hello,

    how to use the FMC (in zynq7000 zedboard) as A/D converter?