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Found 5 results

  1. Dear all, I am working with a video processing platform based on this project: https://www.hackster.io/adam-taylor/creating-a-zynq-or-fpga-based-image-processing-platform-e79394 I am using a Zybo Z7-20 and I am successful to make a simple passthrough buffer using VDMA. The project is described in the link above. However, when I create a project for a simple RGB2GRAY in Vivado HLS to insert block into the previous platform, I can't make it work (link for second project here: https://www.hackster.io/adam-taylor/using-hls-on-an-fpga-based-image-processing-platform-8f029f). U
  2. Hello, dear FPGA enthusiasts! Currently, I have been working with my OV7670 camera and can present it on an HDMI screen. However, this was done without a simulation. What I want to do right now is to use a TPG provided from Xlinix in my design and remove the OV7670 fully. However, the problem is that I really don't know how to go next since I am using uB together with a VDMA and TPG. I know that you can include the ELF file from the uB in order to simulate your design together with uB. My question to you is where I can find C code for the TPG used in the ne
  3. Greetings everyone, This is the first ever post of a beginner who has set on the path to learn embedded systems. Please forgive me if haven't followed rules of posting. I took the embedded system plunge few weeks back. Bought a strong laptop, a Zybo board, OV7670 camera, installed Vivado. Read online tutorials like 'blinking LEDs' and 'HDMI-to-VGA out' (and the others ones in Zynq Book) to get myself accustomed with Vivado etc. [Abbreviations in the text: PS= Processing System, PL= Programmable Logic] I have been visiting a blog lately and have found that quite helpful. A couple of
  4. Hello, I've got some troubles while trying to fully understand the Zybo base system design. I need to replicate in my design (with Vivado 2015.4) the video part of the bsd, with the Axi display control ip. The design works but some points are not very clear to me: I've notice that 2 different clock sources are feed to the PL: (FCLK_CLK0 @ 100 MHz and FCLK_CLK1 @ 150 MHz). What is the reason behind this? Isn't 100 MHz enough for the VDMA? Why an Axi protocol converter is used? The design was build for an older version of Vivado (and ip library)? Thanks
  5. Hi all, I have a Zynq -7000 development board and am using Vivado 2014.4. I have a block design that successfully synthesizes and generates a bitstream. My design uses Xilinx's VDMA core, and I want to use the Xilinx's VDMA driver with it (http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs#AXI VDMA). The driver guide says "The device tree node for AXI VDMA will be automatically generated, if the core is configured in the HW design, using the Device Tree BSP." However, I am having trouble generating a device tree for the design. I have been referencing this http://www.wiki.xilinx.com/Build+Devi