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Found 1 result

  1. Hello, I want to access analogue pin of XADC header to input audio data in FPGA (Virtex VC707 here). But i am getting error in writing bit-stream "Partially routed nets". Design is below: As we provide the pin number and voltage standard in constraint file for pin assignment, but here the I/O Std is faded and cannot be edited. I have also edited constraint file manually but still getting this error. Pin assignment are as under for VC707 Schematics diagram for VC707 Any help will be appreciated. Thanks,