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Found 11 results

  1. Hi Everyone! I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the
  2. Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I wan
  3. Muthupriya Somasundaram posted this question on the Getting started with Vivado and Basys3 video: Hi, I registered in the digilentic forum, but i couldn't able to post any question. I am using a temperature sensor to measure the environment temperature and connected the sensor output to XADC. Now,form which pin do i need to get the binary output and the output will be in how many bits? Thanks in advance! Regards, Priya
  4. hi, I am using PMOD AD1 and PMOD DA2 on ZC702 Eval Board but it dose not work. Befor that I used my code with spart 3a, spartan6 and zedboard and my code work for all of them but when I used that code for the zc702 it dose not work. I use clock division to send 20 Mhz : This is my code: library ieee; use ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; Library UNISIM; use UNISIM.vcomponents.all; entity ad1_da2 is port( SCLK_P : in std_logic; SCLK_n : in std_logic; CS : out std_logic
  5. Hello, The older Atlys boards had a Spartan-6 FPGA which meant the highest progressive resolution supported by the HDMI input and output was 720p (which was always frustrating). I was wondering if that had changed with the newer Series 7 devices like the Zybo or Nexys Video boards? I noticed that hamster was able to get 1080i working. Are SERDES even able to do 1080p theoretically? Thanks for your help! Tim 'mithro' Ansell
  6. hi to all, I am using NETFPGA-1G-CML. I have ported Linux in it and it is working fine.Now i have enable three Ethernet ports. PC --------------------> Board1 (ETH0) 192.168.1.1 192.168.1.2 I have connected my PC to NETFPGA board via telnet. Board1 (ETH1) ----------------> RF Device -------------- Wireless Medium ----------------- RF Device --------------- Board2 (ETH1) 192.168.2.66 192.168.2.67 192.168.2.68 192.168.2.69 Now i can ping from 192.168.2.66 to 192.168.2.67 & 192.1
  7. Hi, It took me a while to get the 7-series OSERDESE2 to simulate and work correctly. If anybody is having similar pain I've put my 10:1 serializer code up on my Wiki. The secret is to use the reset, and then assert CE. http://hamsterworks.co.nz/mediawiki/index.php/OSERDESE2 If you have trouble getting the clocks to work, both 'clk' and 'clk_x5' have to be driven from the same MMCM or a few other possible combinations. It would pay to read the manual (http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf) very carefully, but be careful of a few errors in the docume
  8. Hi everyone ! I need some help please : when I try to implement a counter in active HDL I have this warning message : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I explain : Firstly I have designed a basic counter with Basys2 board : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter_2 is generic (N : integer := 4); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter_2; --}} End of au
  9. Hi all I'm still using a Spartan3e starter kit for various issues (it's aged but still very usefull). For my current project i need to program the Spartan using an external uP that i want to connect to the connector for extended JTag (J28). Now i become unsecure how this should work. The s3e1600 board provides an integrated JTag programmer. Unfortunally it is not documented in the schematic's since it is an Xilinx proprietary design. Moreover J28 does not provide anything like the PGND signal, found i.e. at the Xilinx platform cable USB II. Hence the S3e1600 board can't detect a connected JTag
  10. yasirshah

    Vmodcam resolution

    I am using Digilent Atlys board and Vmodcam in a project. Vmodcam have 1600*1200 maximum resolution. it can be used with 640*480 resolution. I want to know that what is the minimum resolution of Vmodcam. Can it be used for 300*200 resolution?
  11. Hi, I am using PS and custom IPs to do a IR remote demodulation project. I need IR signal from external circuit. My custom IR Demodulator IP does the work and displays the message received. I need to use one of the Pmod banks. My question is can I use standard/ Hi-speed Pmod bank or am I only allowed to use MIO Pmod to receive the input? Also when we generate custom IP we get a signal S_AXI_ACLK signal as clock. How can I find the frequency of this clock signal? Thank You