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Found 11 results

  1. Hi Everyone! I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the clock but its amplitude is Small (around 200 mV compare to the reference voltage of 3.3 V). Moreover, I don't know why, but the clock signal seems to have an offset greater than 1V. I want to know if somebody before me faced the same problem? If yes how did you solve it? The second question I would like to ask is to know if Digilent Engineers checked their pmods on the Zynq 7020? If yes, could you please provide us with a template design as reference to check on our board? Thank you for any suggestions. Hervé
  2. Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I want to call it I just make a instance of this class. In Vivado, when I open my synthesized project and click [Tools ---> Edit devices properties] This is where I select my clock frequency as 50 MHZ { Please see image attached } So my questions are : Is this the proper way to set up a clock using Vivado and the Basys3 Board?In the main page of the Basys3 it says that one can get a clock as high as 450 Mhz but in the options of the [Tools ---> Edit devices properties] I can only find clocks as high as 66 MhzAnd just some basic ones Why Vivado takes sooo long to synthesized, implement and generate the bitstream of an easy and small code? Just implementing in hardware an AND gate takes me 5 minnutes to download the program to the board. Is there a quicker way ? Thanks Forum .
  3. Muthupriya Somasundaram posted this question on the Getting started with Vivado and Basys3 video: Hi, I registered in the digilentic forum, but i couldn't able to post any question. I am using a temperature sensor to measure the environment temperature and connected the sensor output to XADC. Now,form which pin do i need to get the binary output and the output will be in how many bits? Thanks in advance! Regards, Priya
  4. hi, I am using PMOD AD1 and PMOD DA2 on ZC702 Eval Board but it dose not work. Befor that I used my code with spart 3a, spartan6 and zedboard and my code work for all of them but when I used that code for the zc702 it dose not work. I use clock division to send 20 Mhz : This is my code: library ieee; use ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; Library UNISIM; use UNISIM.vcomponents.all; entity ad1_da2 is port( SCLK_P : in std_logic; SCLK_n : in std_logic; CS : out std_logic; -- chip select for ADC(active low) SYNC : out std_logic; -- SYNC for DAC DIN : in std_logic; -- ADC DOUT : out std_logic; -- DAC SCLK : out std_logic; -- ADC SCLK2: out std_logic -- DAC ); end ad1_da2; architecture Behavioral of ad1_da2 is component IBUFGDS is port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- FSM states type state_type is (IDLE, READ_DATA, FUNC, WRITE_DATA); -- initial state signal state : state_type := READ_DATA; -- data from the ADC signal data : std_logic_vector(11 downto 0); -- counter variable signal cnt : integer range 0 to 20 := 0; -- counter for clock division signal clkdiv : integer range 0 to 10; -- new clock from division signal newclk : std_logic := '0'; signal risingedge : std_logic := '1'; -- reset signal signal reset : std_logic := '0'; signal clk : std_logic; begin SCLK <= newclk; SCLK2 <= newclk; begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10) then -- divide 200MHz by 10 risingedge <= risingedge xor '1'; newclk <= newclk xor '1'; clkdiv <= 0; else clkdiv <= clkdiv + 1; end if; end if; end process clock_divide; main : process (CLK, reset) begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10 and risingedge = '1') then case state is when IDLE => CS <= '1'; SYNC <= '1'; if (cnt = 16) then cnt <= 0; state <= READ_DATA; else cnt <= cnt + 1; state <= IDLE; end if; when READ_DATA => CS <= '0'; SYNC <= '1'; cnt <= cnt + 1; if (cnt<4) then cnt <= cnt + 1; state <= READ_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; -- the first 4 bits are 0000 only read the last 12 data(15-cnt) <= DIN; state <= READ_DATA; elsif (cnt = 16) then cnt <= 0; state <= FUNC; end if; -- signal processing would go in this state -- but for now we don't do anything in here when FUNC => CS <= '1'; SYNC <= '1'; cnt <= 0; state <= WRITE_DATA; when WRITE_DATA => CS <= '1'; SYNC <= '0'; if (cnt = 0 or cnt = 1) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt = 2 or cnt = 3) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; DOUT <= data(15 - cnt); state <= WRITE_DATA; elsif (cnt = 16) then cnt <= 0; state <= IDLE; end if; end case; end if; end if; end process main; ibufgds_0 : IBUFGDS port map ( I => SCLK_P, IB => SCLK_n, O => CLK ); end Behavioral; Do you have an idea?
  5. Hello, The older Atlys boards had a Spartan-6 FPGA which meant the highest progressive resolution supported by the HDMI input and output was 720p (which was always frustrating). I was wondering if that had changed with the newer Series 7 devices like the Zybo or Nexys Video boards? I noticed that hamster was able to get 1080i working. Are SERDES even able to do 1080p theoretically? Thanks for your help! Tim 'mithro' Ansell
  6. hi to all, I am using NETFPGA-1G-CML. I have ported Linux in it and it is working fine.Now i have enable three Ethernet ports. PC --------------------> Board1 (ETH0) I have connected my PC to NETFPGA board via telnet. Board1 (ETH1) ----------------> RF Device -------------- Wireless Medium ----------------- RF Device --------------- Board2 (ETH1) Now i can ping from to & but cant ping Now when i remove NETFPGA board and put my laptop on one end and set up same ethernet ip. In this i can easily ping from to Please help me in this regard, very greatful to you. Regards,
  7. Hi, It took me a while to get the 7-series OSERDESE2 to simulate and work correctly. If anybody is having similar pain I've put my 10:1 serializer code up on my Wiki. The secret is to use the reset, and then assert CE. If you have trouble getting the clocks to work, both 'clk' and 'clk_x5' have to be driven from the same MMCM or a few other possible combinations. It would pay to read the manual ( very carefully, but be careful of a few errors in the documentation...
  8. Hi everyone ! I need some help please : when I try to implement a counter in active HDL I have this warning message : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I explain : Firstly I have designed a basic counter with Basys2 board : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter_2 is generic (N : integer := 4); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter_2; --}} End of automatically maintained section architecture counter_2 of counter_2 is signal count: STD_LOGIC_VECTOR(N-1 downto 0); begin process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end counter_2; Then I have produced 24-bit (q(23) downto q(0)) clock divider, my goal is to divide original frequency and obtain 2.98 Hz in using q(23) as output of the clock divider : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity clkdiv2 is port( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end clkdiv2; --}} End of automatically maintained section architecture clkdiv2 of clkdiv2 is signal q: std_logic_vector(23 downto 0); begin process(clk, clr) begin if clr = '1' then q <= X"000000"; elsif clk 'event and clk = '1' then q <= q + 1; end if; end process; clk3 <= q(23); --clk48 <= q(19); --clk190 <= q(17); -- enter your statements here -- end clkdiv2; Finally I have used block diagram of the first counter and the clock divider to light the eight LEDs of Basys 2 as binary counter : ------------------------------------------------------------------------------- -- -- Title : count8_top -- Design : Counter -- Author : Unknown -- Company : Unknown -- ------------------------------------------------------------------------------- -- -- File : c:\My_Designs\Example8\compile\count8_top.vhd -- Generated : Mon Jun 15 22:01:20 2015 -- From : c:\My_Designs\Example8\src\count8_top.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity count8_top is port( clk : in STD_LOGIC; btn : in STD_LOGIC_VECTOR(3 to 3); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end count8_top; architecture count8_top of count8_top is ---- Component declarations ----- component clkdiv2 port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end component; component counter_2 generic( N : INTEGER := 8 ); port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal clk3 : STD_LOGIC; begin ---- Component instantiations ---- U1 : clkdiv2 port map( clk => clk, clk3 => clk3, clr => btn(3) ); U2 : counter_2 port map( clk => clk3, clr => btn(3), q => ld( 7 downto 0 ) ); end count8_top; Finally when I implement the block diagram corresponding to the code above, I have this warning : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I don't understand what does it mean. Could you help me please?
  9. Hi all I'm still using a Spartan3e starter kit for various issues (it's aged but still very usefull). For my current project i need to program the Spartan using an external uP that i want to connect to the connector for extended JTag (J28). Now i become unsecure how this should work. The s3e1600 board provides an integrated JTag programmer. Unfortunally it is not documented in the schematic's since it is an Xilinx proprietary design. Moreover J28 does not provide anything like the PGND signal, found i.e. at the Xilinx platform cable USB II. Hence the S3e1600 board can't detect a connected JTag adapter. I ask myself if this cause any problems when i now use a second (!) JTAG master (via J28) to drive the JTag chain. If i interpret the given schematics correct then i would assume that the integrated JTag controller would be in parallel to J28 (but as i said: this is not documented) which would be asking for trouble . Can anyone provide some help for this ? Thanks in advance Regards AHz
  10. yasirshah

    Vmodcam resolution

    I am using Digilent Atlys board and Vmodcam in a project. Vmodcam have 1600*1200 maximum resolution. it can be used with 640*480 resolution. I want to know that what is the minimum resolution of Vmodcam. Can it be used for 300*200 resolution?
  11. endluri.ram

    Pmod Doubt in ZYBO

    Hi, I am using PS and custom IPs to do a IR remote demodulation project. I need IR signal from external circuit. My custom IR Demodulator IP does the work and displays the message received. I need to use one of the Pmod banks. My question is can I use standard/ Hi-speed Pmod bank or am I only allowed to use MIO Pmod to receive the input? Also when we generate custom IP we get a signal S_AXI_ACLK signal as clock. How can I find the frequency of this clock signal? Thank You