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Found 8 results

  1. Hey, I'm using the VCU118 evaluation board with the Xilinx Ultrascale+ XCVU9P. I'm trying to connect to the FMC-pcam-adapter card. The MC20901 offers a SLVS to LVDS Conversion, so I can connect to the FPGA with LVDS and LVCMOS IO-STANDARDS. I also have a CSI controller with a PPI interface. But, the Vivado's D-PHY IP can't have the HS(high-speed) and LP(lower-power) "split" into two differential pairs. Is there a way to use the Xilinx's D-PHY IP for ultrascale with the board ? or find a simple verilog connverter or DPHY ? Thanks, -Gal
  2. Hi, I'm working on a project based on a Xilinx Ultrascale+. The final board will contain, for JTAG interface, a SMT2-NC device with a USB type-C receptacle. This board should work as "device", and so as Upstream Facing Port (UFP). At the moment, I know how to treat the CC lines (via 5.1 kOhm pull-down resistors) but I still don't understand how to connect (or how to use) the VBUS lines, because the SMT2 is powered from the 3.3V and VREF pins and not VBUS. Can I leave the VBUS lines unconnected or I should follow some specific procedure to connect them? Thanks
  3. We are using a JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs? Thanks, David
  4. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  5. I have generated the bit file from Vivado 18.2 which is installed in windows PC. Now I am trying to generate the SD card image boot file (.bin and .ub files) from petalinux 18.2 installed in a seperate linux PC. I have gone through the ug1144, but I am not able to figure out how to generate. Please share the point wise steps. its very urgent. Thanks in advance.
  6. Hi, My setup is using Avnet Ultrazed board with PMOD AD1. Also I am using Xilinx Vivado & SDK 2019.1. I am successfully being able to use 1 channel of the PMOD AD1. I am trying to use both the ADC channels on the PMOD AD1. As the PMOD libraries has no board support files for the Avnet Ultrazed board I went ahead and created a QSPI IP block to get a single channel working. I am having trouble getting the second channel working. Few doubts I have are: 1. For the QSPI IP block, should I use it in standard mode or Dual SPI mode. (I have set the data pins as MISO. Also selected
  7. Hi All, I have nine 8-bit values that I want to add using the dsp48e2 slice of ZCU104 Evaluation kit. As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html). I want to implement the second approach: "Two of the inputs are free to come from any source and one input comes from an internal DSP48 feedback signal as in a MAC." But after synthesis even the original verilog code is inferring 2 DSP slices. Am I interpreting things wrong or is there any bug in the code? I created this VHDL equivalent of the Verilog code from X
  8. Hi, Im trying to catch an interrupt from an AXI GPIO switch from my board ZCU102. I have created the following design in Vivado: The design is validated so now im using Petalinux to boot linux. I have exported the .hdf file and built petalinux but i can't boot linux.It hangs after that: Exit from FSBL NOTICE: ATF running on XCZU9EG/silicon v1/RTL5.1 at 0xfffe5000 NOTICE: BL31: Secure code at 0xfffc0000 NOTICE: BL31: Non secure code at 0x8000000 NOTICE: BL31: v1.2(release): NOTICE: BL31: Built : 17:17:47, Dec 1 2016 [ 0.000000] Booting Linu