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Found 8 results

  1. Hi, I'm working on a project based on a Xilinx Ultrascale+. The final board will contain, for JTAG interface, a SMT2-NC device with a USB type-C receptacle. This board should work as "device", and so as Upstream Facing Port (UFP). At the moment, I know how to treat the CC lines (via 5.1 kOhm pull-down resistors) but I still don't understand how to connect (or how to use) the VBUS lines, because the SMT2 is powered from the 3.3V and VREF pins and not VBUS. Can I leave the VBUS lines unconnected or I should follow some specific procedure to connect them? Thanks
  2. Hey, I'm using the VCU118 evaluation board with the Xilinx Ultrascale+ XCVU9P. I'm trying to connect to the FMC-pcam-adapter card. The MC20901 offers a SLVS to LVDS Conversion, so I can connect to the FPGA with LVDS and LVCMOS IO-STANDARDS. I also have a CSI controller with a PPI interface. But, the Vivado's D-PHY IP can't have the HS(high-speed) and LP(lower-power) "split" into two differential pairs. Is there a way to use the Xilinx's D-PHY IP for ultrascale with the board ? or find a simple verilog connverter or DPHY ? Thanks, -Gal
  3. We are using a JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs? Thanks, David
  4. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  5. I have generated the bit file from Vivado 18.2 which is installed in windows PC. Now I am trying to generate the SD card image boot file (.bin and .ub files) from petalinux 18.2 installed in a seperate linux PC. I have gone through the ug1144, but I am not able to figure out how to generate. Please share the point wise steps. its very urgent. Thanks in advance.
  6. Hi, My setup is using Avnet Ultrazed board with PMOD AD1. Also I am using Xilinx Vivado & SDK 2019.1. I am successfully being able to use 1 channel of the PMOD AD1. I am trying to use both the ADC channels on the PMOD AD1. As the PMOD libraries has no board support files for the Avnet Ultrazed board I went ahead and created a QSPI IP block to get a single channel working. I am having trouble getting the second channel working. Few doubts I have are: 1. For the QSPI IP block, should I use it in standard mode or Dual SPI mode. (I have set the data pins as MISO. Also selected the number of slaves as 1) 2. In the C code how do I switch between the 2 ADC channels as the 2 slaves are connected to the same chip select. I have set the slave select in initialize as --> XSpi_SetSlaveSelect(SpiInstancePtr, 0x01); 3. Should I use manual slave select or automatic slave select? --> XSpi_SetOptions(SpiInstancePtr, XSP_CLK_ACTIVE_LOW_OPTION | XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION); Thanks!
  7. Hi All, I have nine 8-bit values that I want to add using the dsp48e2 slice of ZCU104 Evaluation kit. As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html). I want to implement the second approach: "Two of the inputs are free to come from any source and one input comes from an internal DSP48 feedback signal as in a MAC." But after synthesis even the original verilog code is inferring 2 DSP slices. Am I interpreting things wrong or is there any bug in the code? I created this VHDL equivalent of the Verilog code from Xilinx. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity tri_adr is GENERIC( CONSTANT SIZEIN : NATURAL := 48; -- Input size CONSTANT SIZEOUT : NATURAL := 48 -- Output size ); PORT( clk : in STD_LOGIC; -- Clock resetn_glb : in STD_LOGIC; -- Global Reset from the Zynq PS resetn_lc : in STD_LOGIC; -- Local Reset if necessary operand_i1 : in STD_LOGIC_VECTOR (SIZEIN-1 downto 0); -- 1st input to dsp operand_i2 : in STD_LOGIC_VECTOR (SIZEIN-1 downto 0); -- 2nd input to dsp operand_i3 : in STD_LOGIC_VECTOR (SIZEIN-1 downto 0); -- 3nd input to dsp avg_out : out STD_LOGIC_VECTOR (SIZEOUT-1 downto 0) -- Averged output ); attribute USE_DSP : string; attribute USE_DSP of tri_adr: entity is "YES"; end ENTITY; architecture behav of tri_adr is signal a : std_logic_vector (26 downto 0); signal b : std_logic_vector (17 downto 0); signal pcout : std_logic_vector (SIZEOUT-1 downto 0); signal avg_t : std_logic_vector (SIZEOUT-1 downto 0); begin avg:PROCESS (clk) --check every clk begin if rising_edge(clk) then if resetn_glb = '0' then --negative assert avg_t <= (OTHERS => '0'); pcout <= (OTHERS => '0'); else pcout <= std_logic_vector((signed(a) * signed(b)) + signed(operand_i1)); avg_t <= std_logic_vector(signed(pcout) + signed(operand_i2) + signed(operand_i3)); -- avg_t <= std_logic_vector(signed(operand_i1) + signed(operand_i2) + signed(operand_i3)); end if; end if; end PROCESS; -- Output result avg_out <= avg_t; end behav; I will be summing three 8-bit numbers using one DSP slice and create a cascaded adder logic to do addittion of all nine values. Thanks in advance. Best regards
  8. Hi, Im trying to catch an interrupt from an AXI GPIO switch from my board ZCU102. I have created the following design in Vivado: The design is validated so now im using Petalinux to boot linux. I have exported the .hdf file and built petalinux but i can't boot linux.It hangs after that: Exit from FSBL NOTICE: ATF running on XCZU9EG/silicon v1/RTL5.1 at 0xfffe5000 NOTICE: BL31: Secure code at 0xfffc0000 NOTICE: BL31: Non secure code at 0x8000000 NOTICE: BL31: v1.2(release): NOTICE: BL31: Built : 17:17:47, Dec 1 2016 [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.4.0 ([email protected]) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #2 SMP Thu Dec 1 17:19:05 CET 2016 [ 0.000000] Boot CPU: AArch64 Processor [410fd034] [ 0.000000] earlycon: Early serial console at MMIO 0xff000000 (options '115200n8') [ 0.000000] bootconsole [uart0] enabled [ 0.000000] cma: Reserved 128 MiB at 0x0000000078000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] PERCPU: Embedded 15 pages/cpu @ffffffc87ff71000 s23936 r8192 d29312 u61440 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: enabling workaround for ARM erratum 845719 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1034240 [ 0.000000] Kernel command line: earlycon=cdns,mmio,0xFF000000,115200n8 [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 0.000000] software IO TLB [mem 0x73fff000-0x77fff000] (64MB) mapped at [ffffffc073fff000-ffffffc077ffefff] [ 0.000000] Memory: 3908832K/4194304K available (7061K kernel code, 520K rwdata, 2692K rodata, 13604K init, 348K bss, 154400K reserved, 131072K cma-reserved) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbdffff0000 ( 247 GB) [ 0.000000] vmemmap : 0xffffffbe00000000 - 0xffffffbfc0000000 ( 7 GB maximum) [ 0.000000] 0xffffffbe00000000 - 0xffffffbe1dc00000 ( 476 MB actual) [ 0.000000] fixed : 0xffffffbffa7fd000 - 0xffffffbffac00000 ( 4108 KB) [ 0.000000] PCI I/O : 0xffffffbffae00000 - 0xffffffbffbe00000 ( 16 MB) [ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB) [ 0.000000] memory : 0xffffffc000000000 - 0xffffffc880000000 ( 34816 MB) [ 0.000000] .init : 0xffffffc000a07000 - 0xffffffc001750000 ( 13604 KB) [ 0.000000] .text : 0xffffffc000080000 - 0xffffffc000a06ff4 ( 9756 KB) [ 0.000000] .data : 0xffffffc001762000 - 0xffffffc0017e4360 ( 521 KB) [ 0.000000] Hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 64. [ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4 [ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns [ 0.000003] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns [ 0.008316] Console: colour dummy device 80x25 [ 0.012575] console [tty0] enabled [ 0.015942] bootconsole [uart0] disabled If i boot petalinux by qemu i manage boot linux, but the interrupt i defined in the design does not appear on the system I'm beggining with embedded linux so i don't know if i'm missing something. Any idea?? pl.dtsi zynqmp.dtsi pcw.dtsi system-top.dts system-conf.dtsi