Search the Community

Showing results for tags 'udp'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 6 results

  1. Dear Team, We have established Ethernet communication on Arty-7 35 T for FPGA to PC (Transmission) and PC to FPGA (Reception). We have done RTL design without using micro-blaze and On system side we are using Visual studio for sending commands to FPGA using socket programming. We are facing following problems which are given below : FPGA to PC communication works perfectly for any IP address, but When we send command from socket for PC to FPGA communication, Ethernet on FPGA only listen to xxx.xxx.1.255 - broad cast IP. FPGA does not listen to any other value than 255. What could be reason behind this? Another problem we observed related to wire shark. While having Ethernet communication, If we close wire-shark, FPGA stops sending data. We are not able figure the main cause.
  2. Hello All, I am currently working on Nexys Video Ethernet. I want to transmit and recieve UDP packets between PC and Nexys Video FPGA . Is it possible to perform without Microblaze? How to send UDP Packets from PC to FPGA.?
  3. Hello i'm using 2 ZedBoards cards with Vivado 2017.4 (for the record - i've tried to work with 2018.1 but from some reason there was a problem with the wifi's library and someone here at the forum suggest to work with 2017.4. link to this post: https://forum.digilentinc.com/topic/17224-pmod-wifi-sdk-problem/#comment-42818 the 2 ZedBoards are connected with the PmodWiFi module, this module has been tested and the hardware is working fine. my goal is to transfer a 120*160 matrix of integers from one zedboard to another. i've succeded to transfer string or several integers between the boards. the project are based on the tcp client and tcp server which exists in the examples inside PmodWiFi library. (also tried the UDP examples, didn't work). i'm sending each time an array of 160 elements. so in total in each transfer there are 640 bytes of data. the function being used is: tcpSocket.writeStream((u8*)mat,160*4)) in while loop until 120 transfers are being made. the current situation is that i'm not getting all the packets at the second card. in average 15-20 packets from total 120 packets are recieved. after a research i've made, i get an offer to put the function -> DEIPck::periodicTasks(); after every write stream but it didn't work. putting sleep(2) after each send also didn't solve the issue. attached a screenshot of the relevant code which will help to explain how the send data works. i'll be glad if someone could help with this topic or refer me to relevant project.
  4. A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: 192.168.1.10 Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use any input or output FIFO's as elesticity buffers,both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes, which allows better resource utilisation at the price of, probably, more complex design architecture. Design is implemented in VHDL using ISE by Xilinx. Below there are the source files for the echo-server projects along with .m file to transmit/receive data using MatLAB. Figure "wireshark_capture" illustrates the data traffic between FPGA board and data server (MatLAB); Figure "TxRx_Error" compares transmitted data against the data received from the board. UDP echo-server manual.7z UDP echo-server.7z
  5. Hi, Currently I have an issue when I connect the Wi-Fire to wireless network using UDP protocol. It will be helpful if is some information about the fuctions availables on the libraries <DEIPcK.h> and <DEWFcK.h>. On this moment my target is to solve the error received from "IsIPStatusAnError(status)". I'm not sure which configurations are necessary to solve the error, the error is attached . This error comes when the following code trys to work. Could you give me information available to use the UDP protocol used on the sketch named "UDPEchoClient .pde"? Code involved in Yellow case RESOLVEENDPOINT: if(deIPcK.resolveEndPoint(szIPServer, portServer, epRemote, &status)) { if(deIPcK.udpSetEndPoint(epRemote, udpClient, portDynamicallyAssign, &status)) { state = WRITE; } } // alway check the status and get out on error if(IsIPStatusAnError(status)) { Serial.print("Unable to resolve endpoint, error: 0x"); Serial.println(status, HEX); state = CLOSE; } break;
  6. Hi -- I have a WF32. I can get it connected and do point to point UDP just fine. I need to receive a multicast UDP stream from a PC. I got this working on a WiFi Flyport (openpicus.com) but the PIC was underpowered... Does DNETcK/DWIFIcK support multicast and if so are there examples available?? Thanks Bill