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Found 87 results

  1. Hi, I'm using JTAG-SMT3-NC for JTAG and UART on a custom board. One of the boards has a very strange behavior when sending UART serial to the board. The character 'U' doesn't work, but all other keys work fine. Digging into it a bit further, I can see with a scope that the UART signal is incorrect for the letter 'U'. Please see attached scope plot. The upper (white) trace is when the 'U' key is pressed. Please compare this to the lower (yellow) is the 'A' key. Manually decoding, the 'A' waveform is correct (0x41), but the 'U' is incorrect (0xd5 instead of 0x55). A few other notes: Same behavior on two totally separate laptops (windows10) Same behavior at different baud rates. 115200 baud, 1N8 normally used. The 'U' key works as expected on ~10 other boards we used. Seems like something "happened" with this one. All other letters appear correct, and have their MSB cleared. Could anyone think what might cause this behavior? UART trace U vs A.bmp
  2. Disclaimer: I'm not an expert, just a student working on a school project. My zybo z7 board stopped showing up as /dev/ttyUSBx on my linux vm when connected using the UART microUSB port. On my windows host the com port does show up but I cannot open a connection with putty (115200 8n1), no error info or strange characters, just an error sound effect with no explanation. I tried everything on the pc side (driver reinstall, reboot, enable/disable port, different ports, different cables) but I suspect that it is the board not communicating. I use external power with WALL selected and booted from an sd card with a 500 mb fat32 partition with a boot and image file generated with xilinx petalinux which were not changed from when everything worked fine. There is also a 3gb ext4 partition where the fs is. The only thing that changed before the problem occured is that a few to-be-tested precompiled kernel modules where added to the ext fs in the home folder. Other students with the same set-up do not have this problem. I tried different sd cards and remade the partitions and redid the boot/image/fs generation but no success. When booting from QSPI the example program works fine so I don't think the board is broken (The serial com doesn't work in QSPI either but I don't know if it's supposed to). Maybe it needs some kind of factory reset? Is there a way to confirm if the microUSB port is working? Help will be appreciated. btw: upon startup I can see the RX led flickering but never the TX led
  3. Hello All, I have a Coraz7-10 board where I have the uart working in send mode, but not in receive mode. The uart is configured to operate on an interrupt, and I'm using the xilinx example code. I have modified just slightly with some debug messages and the recv handler. Basically, I just want to "set" a signal when then handler occurs, and "reset" it in the main() loop. In the handler itself, I am just checking to see if the received data makes it there, confirming in debugger view of SDK with watch variables. However, rx data is never present. I'm new to Zync, so if there are any suggestion, much appreciated. Thanks. James
  4. Dear All, I have currently finished a PL program for signal processing and hardware controlling on the Zybo Z7010 board. Now, I want to ensure that some parameters can be easily modified by the user on a computer. Thus, I would like to use the USB -- micro-USB cable to instaure a communication between the user and the board. After some reading, I understand that I have to use the PS if I want to go through the micro-USB UART port (I have not yet used the PS in my project...). Hence, I need two things: - Instantiating the UART interface and writing the C/C++ script to ensure communication between User and PS - Creating a write/read connection between PS and PL to modify the parameters after reception by the PS. How should I proceed? As usual, feel free to ask for any further information. P.S. : Until now, I have used only Verilog and VHDL code to make the whole project run and am very uncomfortable with the "Block design" tool, so please be as specific as possible if block design is required (or faster/simpler...) Thank you very much,
  5. Hi, While there are many examples showing a basic Hello World using a Zynq UART, how do we read in data from the console using the same UART? Can anyone please guide me to the right example. I cudn't find one.
  6. Hi,guys! I'm currently working on how to send character"hello" to FPGA and then transmit "hello" back to my PC. But it seems I only can send some characters to my board and cannot receive the chracters back to PC. I wonder how to build my code in python to get the characters back to my PC. The attachment is my code(PYTHON) and result of runing. import serial ser = serial.Serial("com9",9600,timeout=0.25) print( print(ser.port) c=input("hello") b=ser.isOpen() ser.write(c.encode()) print(s) print(b) ser.close() Thanks, Dehao
  7. I am trying to use a DAQ to analyze I2C, SPI, and UART signals and then classify them, so they have to be the actual output signals from the Cora Z7 board. However, I am limited due to the project itself to use only the General Purpose I/O pins (IO0-IOA(IO42)). Is it possible to funnel the SPI, I2C, and UARt signals through these pins, or can you only use the specified pins, such as SDA/SCL, MISO/MOSI, or the USB UART bridge to do this?
  8. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin // then count value flip over to zero, then make led on or off led <= ~led; // in the always loop, it needs to use registers end count <= count +1; // add the count value until it flips over to zero end else begin // if there is no key to be pressed, init the led to off state; led <=0; count <=1; end endmodule and I included this module in IP design. and the errors were like below. before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed' I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? Thank you for your kind answers, ...
  9. i wanted to interface multiple digital serialiser with arty A7 35T board through pmod pins. And transmit the same data through UART. help me with the verilog code and other resource.
  10. The protocol options and features in WaveForms are great and do just what I need. The only issue it looks like Waveforms only supports one Protocol window, hence 1 UART. I need to monitor serial communications between two devices, which means I need two RX inputs. Is there a way to achieve this with the latest version?
  11. Is it possible to decode scope data using one of the "protocols"? I often need to analyze scope data as inverted UART data (e.g an RS-232 async serial signal).
  12. Hello, I’m having problems with sending large amount of data from ZYBO to a computer. For example, when I tried to send image data (640x480) at the maximum baud rate, the computer didn’t receive all data. But when baud rate was set to 256000, all data were received. It seems like UART buffer is overflowing. How to solve this problem? Best regards, Toni
  13. Can anyone suggest me how to program the UART/USB available in the ZYBO Z7 board and use it as a port to feed the data from the PC/SERVER ?
  14. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from After installing as described in I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  15. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port( clk : in std_logic; rst : in std_logic; start : in std_logic; input : in std_logic_vector(7 downto 0); done : out std_logic; output : out std_logic; showstates: out std_logic_vector(3 downto 0) ); end entity; architecture dataflow of rs232_omo is type states is (idle_state,start_state,send_state,stop_state); signal present_state,next_state : states; signal data,data_next : std_logic; begin process(clk,rst) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin if rst='1' then present_state<=idle_state; count:=0; data<='1'; elsif rising_edge(clk) then present_state<=next_state; count:=count+1; index:=index+1; data<=data_next; end if; end process; process(present_state,data,clk,rst,start) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin done<='0'; data_next<='1'; case present_state is when idle_state => showstates<="1000"; data_next<='1'; if start='1' and rst='0' then count:=count+1; if count=clk_max then next_state<=start_state; count:=0; end if; end if; when start_state => showstates<="0100"; data_next<='0'; count:=count+1; if count=clk_max then next_state<=send_state; count:=0; end if; when send_state => showstates<="0010"; count:=count+1; data_next<=input(index); if count=clk_max then if index=7 then index:=0; next_state<=stop_state; else index:=index+1; end if; count:=0; end if; when stop_state => showstates<="0001"; count:=count+1; if count=clk_max then next_state<=idle_state; done<='1'; count:=0; end if; end case; end process; output<=data; end architecture; Constraints: set_property PACKAGE_PIN V17 [get_ports {input[0]}] set_property PACKAGE_PIN V16 [get_ports {input[1]}] set_property PACKAGE_PIN W16 [get_ports {input[2]}] set_property PACKAGE_PIN W17 [get_ports {input[3]}] set_property PACKAGE_PIN W15 [get_ports {input[4]}] set_property PACKAGE_PIN V15 [get_ports {input[5]}] set_property PACKAGE_PIN V14 [get_ports {input[6]}] set_property PACKAGE_PIN W13 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[0]}] set_property PACKAGE_PIN L1 [get_ports {showstates[3]}] set_property PACKAGE_PIN P1 [get_ports {showstates[2]}] set_property PACKAGE_PIN N3 [get_ports {showstates[1]}] set_property PACKAGE_PIN P3 [get_ports {showstates[0]}] set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN R2 [get_ports rst] set_property PACKAGE_PIN T1 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports done] set_property IOSTANDARD LVCMOS33 [get_ports output] set_property PACKAGE_PIN V3 [get_ports done] set_property PACKAGE_PIN V13 [get_ports output] My testbench simulation got attached. And on-board, apparently I stuck with 'idle_state'. For any kind of help, I thank y'all in advance.
  16. Greetings, I would like to replicate the result being captured by the Logic Analyzer GUI here: Is it possible to combine the Digital_UART and DigitalIn Functions to create a VB6 wrapper that will display results like in the GUI? I'm not sure if my hunch is correct or possible, but since the UART is a setting in the Logic Analyzer GUI: I suspect that we can implement the Digital_UART function into one of the DigitalIn APIs available in order to create a VB6 program to receive data that is composed of both: 1. Captured Bit Sequence of character sent (Like in the Data Line of the WaveForms GUI) , and 2. Its equivalent ASCII format (Like in the UART Line of the WaveForms GUI). Any advice? Regards, Lesiastas
  17. Greetings, Forgive me, but I'm not that knowledgeable in python and I'm having trouble understanding the "create_string_buffer" argument in the sample code. How do you declare this "create_string_buffer" statement into its VB6 equivalent? Sincerely yours, Lesiastas
  18. Hello, I was hoping to use your uC32 board to control 4 stepper motor drivers and to provide debug information over serial back to a PC. Unfortunately though the UART routine implemented in HardwareSerial only has a buffered RX implementation and not a buffered TX implementation. This means that at lower baud rates or with larger debug payloads the time to send the data into the serial line can take a rather long time. I looked around online and I can't find any pre-built libraries that implement an IRQ based UART TX Buffer on the PIC32 that would be compatible with the framework supplied by chipkit. I found one but it's based on entirely different compiler and set of libraries so doesn't appear compatible. The regular core arduino HardwareSerial library was updated at some point to support a TX buffer, would diligent consider updating the HardwareSerial implementation that comes with chipkit for the uC32 to also support a TX buffer? UPDATE: I managed to implement a TX buffer without too much difficulty, not sure how robust it is though, this fixed my issue by eliminating blocking serial writes. This might be a useful feature improvement you would consider for the future.
  19. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem. So the data transmission is initiated by NODE A and the control is with NODE A. NODE A will Enable the data transmission for all four UARTs. Now the problem which i am facing is, when NODE A enables the transmission for any two of the UART lines the data transmission is smooth, the problem arises only when i enable the other two. Which means the zybo is not capable of attending to those interrupts which is simultaneously coming from NODE A through four UART lines. My data contains Start byte and Stop byte, Both Start and stop byte are same character. I will attach a my Interrupt handler for reference. **************NOTE************** UART IP on PL side : UART16550 Type of UART : Interrupt driven. Software used : Vivado 2018.3 and SDK Bare metal software. UART interrupt priority : equal priority for all four UARTs. ********************************** I am not very sure about how to use four UARTs efficiently with my Zybo . Please help me with the problem, any inputs from your side will be appreciated. The following is my UART interrupt handler. *************************************************************************** static void RW1RecvHandler(void *CallBackRef, unsigned int EventData) { int i, ch, RecvCount, index; RecvCount = EventData; // repeat this loop for all chars received, i.e., for all ReceivedCount i = 0; while (i < RecvCount) { ch = RW1_RecieveBuffer[i++]; // get the received char from the buffer if(RW1_Start_byte_flag == 1) { // Stop Byte Check for RW1 if (ch == 0xc0) { // Ignore one of the two successive start byte characters if (RW1_ReceivedCount > 1) { RW1_Start_byte_flag = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; RW1_Frame_complete_flag = 1; } } else { if ((index = RW1_ReceivedCount) < TEST_BUFFER_SIZE) { RW1_Buffer[index] = ch; RW1_ReceivedCount++; } else RW1_Start_byte_flag = 0; } } // Start Byte Check for RW1 else if (ch == 0xc0) { RW1_Start_byte_flag = 1; RW1_ReceivedCount = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; // Note the cpu time when first character is received XTime_GetTime(&t_start_RW1); RW1_Frame_complete_flag = 0; } } if(RW1_Frame_complete_flag == 0) { // set up the buffer for next char in interrupt mode XUartNs550_Recv(&RW1, RW1_RecieveBuffer, 1); } } Thanks & Regards Ajeeth Kumar
  20. Hi, I've opened the Cora-Z7-10-base-linux project in Vivado 2017.4 (to avoid any version-dependent issues) on Linux, and I was hoping to be able to route the UART 1 device from the ZYNQ7 Processing System out to the outside world. Ideally I'd like it to be wired up to the DP0 and DP1 pins, as I have a nice little Arduino Click2 adapter that I can put an RS485 Click board one. However, being very new to all this Zynq/Cora/Vivado stuff, I'm not sure how to do it. I started off (with a bit of advice from someone who knows more about this than me, but was rushing off home!) by opening the ZYNQ7 Processing System for re-customisation, and, in the Peripheral I/O Pins view, clicking on the EMIO button at the end of the UART1 row, and clicking OK. At this point, the block design is updated and UART_1 shows up on the ZYNQ7 Processing System block. Then I expanded UART_1 and, for each of the signals, right clicked and selected "Make external" before saving the block design and doing "Generate Block Design" again. The signal names related to UART 1 then showed up in the wrapper VHDL. Next, to try to map then to the Arduino I/O pins, I edited the constraints file by uncommenting and updating the ck_io0 and ck_io1 lines to be as follows: set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { UART1_RX_0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { UART1_TX_0 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1] Save, and "Generate Bitstream" to make all the steps run.. Unfortunately it breaks here with the following errors and critical warnings in the Messages view: Implementation Design Initialization [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port UART1_RX_0 can not be placed on PACKAGE_PIN U14 because the PACKAGE_PIN is occupied by port shield_dp0_dp13_tri_io[0] ["/home/jmccabe/work/Cora-Z7-10/Cora-Z7-10-base-linux/src/constraints/Cora-Z7-10-Master.xdc":92] Place Design [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 1 sites. Term: UART1_RX_0 [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 33 | LVCMOS33(33) | | | +3.30 | YES | | | 35 | 50 | 41 | LVCMOS33(41) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 74 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | Shield_I2C_scl_io | LVCMOS33 | IOB_X0Y1 | P16 | | | | Shield_I2C_sda_io | LVCMOS33 | IOB_X0Y2 | P15 | | | | Shield_SPI_io0_io | LVCMOS33 | IOB_X0Y29 | W15 | | | | Shield_SPI_io1_io | LVCMOS33 | IOB_X0Y46 | T12 | | | | d_dp0_dp13_tri_io[0] | LVCMOS33 | IOB_X0Y28 | U14 | | | | _dp0_dp13_tri_io[10] | LVCMOS33 | IOB_X0Y27 | U15 | | | | d_dp0_dp13_tri_io[1] | LVCMOS33 | IOB_X0Y43 | V13 | | | | d_dp0_dp13_tri_io[2] | LVCMOS33 | IOB_X0Y40 | T14 | | | | d_dp0_dp13_tri_io[3] | LVCMOS33 | IOB_X0Y39 | T15 | | | | d_dp0_dp13_tri_io[4] | LVCMOS33 | IOB_X0Y8 | V17 | | | | d_dp0_dp13_tri_io[5] | LVCMOS33 | IOB_X0Y7 | V18 | | | | d_dp0_dp13_tri_io[6] | LVCMOS33 | IOB_X0Y11 | R17 | * | | | d_dp0_dp13_tri_io[7] | LVCMOS33 | IOB_X0Y37 | R14 | * | | | d_dp0_dp13_tri_io[8] | LVCMOS33 | IOB_X0Y24 | N18 | | | | _dp26_dp41_tri_io[0] | LVCMOS33 | IOB_X0Y12 | R16 | | | | _dp26_dp41_tri_io[1] | LVCMOS33 | IOB_X0Y45 | U12 | | | | _dp26_dp41_tri_io[2] | LVCMOS33 | IOB_X0Y44 | U13 | | | | _dp26_dp41_tri_io[3] | LVCMOS33 | IOB_X0Y30 | V15 | | | | _dp26_dp41_tri_io[4] | LVCMOS33 | IOB_X0Y32 | T16 | | | | _dp26_dp41_tri_io[5] | LVCMOS33 | IOB_X0Y31 | U17 | | | | _dp26_dp41_tri_io[6] | LVCMOS33 | IOB_X0Y10 | T17 | | | | _dp26_dp41_tri_io[7] | LVCMOS33 | IOB_X0Y9 | R18 | | | | _dp26_dp41_tri_io[8] | LVCMOS33 | IOB_X0Y3 | P18 | | | | _dp26_dp41_tri_io[9] | LVCMOS33 | IOB_X0Y4 | N17 | | | | user_dio_tri_io[10] | LVCMOS33 | IOB_X0Y17 | W20 | | | | user_dio_tri_io[2] | LVCMOS33 | IOB_X0Y22 | N20 | | | | user_dio_tri_io[3] | LVCMOS33 | IOB_X0Y21 | P20 | | | | user_dio_tri_io[4] | LVCMOS33 | IOB_X0Y23 | P19 | | | | user_dio_tri_io[5] | LVCMOS33 | IOB_X0Y49 | R19 | | | | user_dio_tri_io[6] | LVCMOS33 | IOB_X0Y20 | T20 | | | | user_dio_tri_io[7] | LVCMOS33 | IOB_X0Y0 | T19 | | | | user_dio_tri_io[8] | LVCMOS33 | IOB_X0Y19 | U20 | | | | user_dio_tri_io[9] | LVCMOS33 | IOB_X0Y18 | V20 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | Shield_SPI_sck_io | LVCMOS33 | IOB_X0Y62 | H15 | | | | Shield_SPI_ss_io | LVCMOS33 | IOB_X0Y88 | F16 | | | | btns_2bits_tri_i[0] | LVCMOS33 | IOB_X0Y91 | D20 | | | | btns_2bits_tri_i[1] | LVCMOS33 | IOB_X0Y92 | D19 | | | | rgb_led[0] | LVCMOS33 | IOB_X0Y55 | L15 | | | | rgb_led[1] | LVCMOS33 | IOB_X0Y68 | G17 | | | | rgb_led[2] | LVCMOS33 | IOB_X0Y58 | N15 | | | | rgb_led[3] | LVCMOS33 | IOB_X0Y99 | G14 | | | | rgb_led[4] | LVCMOS33 | IOB_X0Y56 | L14 | | | | rgb_led[5] | LVCMOS33 | IOB_X0Y53 | M15 | | | | _dp0_dp13_tri_io[11] | LVCMOS33 | IOB_X0Y75 | K18 | | | | _dp0_dp13_tri_io[12] | LVCMOS33 | IOB_X0Y72 | J18 | | | | _dp0_dp13_tri_io[13] | LVCMOS33 | IOB_X0Y61 | G15 | * | | | d_dp0_dp13_tri_io[9] | LVCMOS33 | IOB_X0Y83 | M18 | | | | dp26_dp41_tri_io[10] | LVCMOS33 | IOB_X0Y84 | M17 | | | | dp26_dp41_tri_io[11] | LVCMOS33 | IOB_X0Y77 | L17 | | | | dp26_dp41_tri_io[12] | LVCMOS33 | IOB_X0Y73 | H17 | | | | dp26_dp41_tri_io[13] | LVCMOS33 | IOB_X0Y71 | H18 | | | | dp26_dp41_tri_io[14] | LVCMOS33 | IOB_X0Y67 | G18 | | | | dp26_dp41_tri_io[15] | LVCMOS33 | IOB_X0Y81 | L20 | | | | user_dio_tri_io[0] | LVCMOS33 | IOB_X0Y82 | L19 | | | | user_dio_tri_io[11] | LVCMOS33 | IOB_X0Y80 | K19 | | | | user_dio_tri_io[1] | LVCMOS33 | IOB_X0Y86 | M19 | | | | vaux0_v_n | LVCMOS33 | IOB_X0Y97 | B20 | | | | vaux0_v_p | LVCMOS33 | IOB_X0Y98 | C20 | | | | vaux12_v_n | LVCMOS33 | IOB_X0Y69 | F20 | | | | vaux12_v_p | LVCMOS33 | IOB_X0Y70 | F19 | | | | vaux13_v_n | LVCMOS33 | IOB_X0Y63 | G20 | | | | vaux13_v_p | LVCMOS33 | IOB_X0Y64 | G19 | | | | vaux15_v_n | LVCMOS33 | IOB_X0Y51 | J16 | | | | vaux15_v_p | LVCMOS33 | IOB_X0Y52 | K16 | | | | vaux1_v_n | LVCMOS33 | IOB_X0Y93 | D18 | | | | vaux1_v_p | LVCMOS33 | IOB_X0Y94 | E17 | | | | vaux5_v_n | LVCMOS33 | IOB_X0Y65 | H20 | | | | vaux5_v_p | LVCMOS33 | IOB_X0Y66 | J20 | | | | vaux6_v_n | LVCMOS33 | IOB_X0Y59 | J14 | | | | vaux6_v_p | LVCMOS33 | IOB_X0Y60 | K14 | | | | vaux8_v_n | LVCMOS33 | IOB_X0Y95 | A20 | | | | vaux8_v_p | LVCMOS33 | IOB_X0Y96 | B19 | | | | vaux9_v_n | LVCMOS33 | IOB_X0Y89 | E19 | | | | vaux9_v_p | LVCMOS33 | IOB_X0Y90 | E18 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances It seems that I naively thought that those lines being commented out meant those signals weren't connected (shows how little I know!). Can anyone give me any pointers on how to overcome this, or how I should be doing this? Any help will be very gratefully appreciated. John
  21. Hello, I am trying to send a character to FPGA from PC hyper terminal , for eg : 's' to start other processes in FPGA like initiating generation of CCD signals and sampling ADC et al and a different ascii character to stop the processes. I am able to send a ASCII character from PC hyper terminal and receive binary value it on FPGA LED's however I'm unable to use this for control. Please find my top level code below. 'Start' signal is to be controlling the initiation of other processes. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; use IEEE.MATH_REAL.ALL; ----------------------------------------------------- entity top_module is port( --------------------UART_GUI------------------------------- RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); ---COMMON INPUTS--- clk, rst : in std_logic; --send_ccd : in std_logic;---------------CCD control SH,ICG,master_ccd_clock : out std_logic; ----FOR AD7980-------- --sample: in std_logic; -------------- to start sampling samp_ind: out std_logic;---------------indicates sampling in process adc_cnv : out std_logic;---------------cnv for AD7980 adc_clk : inout std_logic;--------------SPI clock adc_miso : in std_logic;------------------output from AD7980 -------FIFO SIGNALS-------- WriteEn , ReadEn : in std_logic; -------------fifo controls full, empty : out std_logic ------------------indicates fifo status ); end top_module; architecture structural of top_module is ----------------------------------------------------------------------------UART CONTROL GUI------------------------------------- component receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END component receiver; ----------------------------------------FIFO COMPONENT DECLARATION ----------------------------------------------------------------- component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; -------------------------------------------------------------------------------------------------------------------------- signal fifo_data_out : STD_LOGIC_VECTOR (15 downto 0); signal adc_out : std_logic_vector(15 downto 0); signal start :std_logic; -------------------------UART_RX_FOR CONTROL_ OF_PROCESSES--------------------------------------------------------------- process(Clk,RxData) begin if RxData = "01110011" then start <= '1' ; elsif RxData = "01110000" then start <= '0'; else start <= '0'; end if; end process; --------------------AD7980PORTMAP---------------------------------------------------------------------------------- AD7980 : entity work.AD7980 port map ( clock => clk, sample => start, -- data output Dout => adc_out(15 downto 0), samp_ind => samp_ind, -- ADC connection adc_miso => adc_miso, adc_cnv => adc_cnv, adc_clk =>adc_clk ); ---------------------------------------------FIFO PORTMAP---------------------------------------------------------------- fifo_i: component fifo port map ( clk_100MHz => clk, din_0(15 downto 0) => adc_out(15 downto 0), dout_0(15 downto 0) => fifo_data_out(15 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); ccd_control : entity work.TCD1103GFG port map ( clock => clk, send => start, SH => SH, ICG => ICG, master_ccd_clock => master_ccd_clock); ---------------------------------------------------------------UART GUI CONTROL--------------------------------------- uart_gui : entity work.receiver port map ( clk => clk, reset => rst, RxD => RxD, RxData => RxData ); end structural; Here is the UART receiver open source code I'm using that works LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END receiver; ARCHITECTURE behavioural OF receiver IS SIGNAL shift : STD_LOGIC; SIGNAL state : STD_LOGIC; SIGNAL nextstate : STD_LOGIC; SIGNAL bitcounter : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL samplecounter : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL counter : STD_LOGIC_VECTOR(13 DOWNTO 0); SIGNAL rxshiftreg : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL clear_bitcounter : STD_LOGIC; SIGNAL inc_bitcounter : STD_LOGIC; SIGNAL inc_samplecounter : STD_LOGIC; SIGNAL clear_samplecounter : STD_LOGIC; constant clk_freq: integer := 100000000; constant baud_rate :integer := 9600; constant div_sample :integer := 4; constant div_counter :integer := (clk_freq/(baud_rate*div_sample)); constant mid_sample : integer := (div_sample/2); constant div_bit : integer := 10; BEGIN RxData <= rxshiftreg(8 DOWNTO 1); PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN state <= '0'; bitcounter <= "0000"; counter <= "00000000000000"; samplecounter <= "00"; ELSE counter <= counter + "00000000000001"; if (counter>= div_counter - 1) then counter <= "00000000000000"; state <= nextstate; IF (shift = '1') THEN rxshiftreg <= (RxD & rxshiftreg(9 DOWNTO 1)); END IF; IF (clear_samplecounter = '1') THEN samplecounter <= "00"; END IF; IF (inc_samplecounter = '1') THEN samplecounter <= samplecounter + "01"; END IF; IF (clear_bitcounter = '1') THEN bitcounter <= "0000"; END IF; IF (inc_bitcounter = '1') THEN bitcounter <= bitcounter + "0001"; END IF; END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN shift <= '0'; clear_samplecounter <= '0'; inc_samplecounter <= '0'; clear_bitcounter <= '0'; inc_bitcounter <= '0'; nextstate <= '0'; CASE state IS WHEN '0' => IF (RxD = '1') THEN nextstate <= '0'; ELSE nextstate <= '1'; clear_bitcounter <= '1'; clear_samplecounter <= '1'; END IF; WHEN '1' => nextstate <= '1'; IF (samplecounter = (mid_sample - 1)) THEN shift <= '1'; END IF; IF (samplecounter = (div_sample - 1)) THEN IF (bitcounter = (div_bit - 1)) THEN nextstate <= '0'; END IF; inc_bitcounter <= '1'; clear_samplecounter <= '1'; ELSE inc_samplecounter <= '1'; END IF; WHEN OTHERS => nextstate <= '0'; END CASE; END IF; END PROCESS; end behavioural; I'm unsure if the issue is because of the number of clock cycles for which the character 's' exists. Please help me understand the miss here.
  22. Hello, I've been to set up a new Zybo board but I'm stuck with a serial port issue. I built my design with the provided board files in Vivado 2017.4. I tried a simple "hello world" in SDK but only got a bunch of unprintable characters. I have Tera Term set up for 115200, 8-bit, 1 stop, no parity. I tried Putty as well and had the same results. I verified the Vivado project is using UART1 MIO48..49. I intermittently can get the correct initialization message from the preloaded QSPI image, but most times it's unprintable characters. I also tried the pre-built Linux from the 2017.4 Zybo Petalinux BSP with the same result. It's definitely booting, but the terminal output is unprintable characters. Other things to note: * I'm running off USB power. I'm plugged directly into my laptop * Sometimes pressing the Reset button makes the PGOOD LED flicker until power cycled Thank you Richard
  23. Hi, I have designed an UART core without any flow control for use with FPGA devices when communicating with LabVIEW. I am looking for a way to receive (from FPGA to LabVIEW) data fast and correctly, hence I am investigating the following configurations for setting the VISA READ when to start or stop reading UART bytes: 1-with termination char: this is very tricky in the binary world as are the FPGAs, because it can trigger false stops sooner than expected. A solution will be to use a custom 3 termination chars like "/n/n/n" and LabVIEW will read till will receive this sequence. 2- by counting the received bytes and compare them with the expected number of bytes and the process the data. 3- using flow control. Which approach is better to be used? Or do you have another ideas? Thanks, V.M.
  24. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf
  25. Hello, I am new to ZYBO board. I am working on a project where I want to control a sensor from my ZYBO board using UART and receive the data from the sensor via SPI. I searched for the reference design, tutorials online to get started with, but I could not find any. Can anyone point me in the right direction where I can refer to and implement my work? THANK YOU. This is my aim as shown below. I want Zybo to be the main host, not my PC.