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Found 69 results

  1. Hello, I am trying to send a character to FPGA from PC hyper terminal , for eg : 's' to start other processes in FPGA like initiating generation of CCD signals and sampling ADC et al and a different ascii character to stop the processes. I am able to send a ASCII character from PC hyper terminal and receive binary value it on FPGA LED's however I'm unable to use this for control. Please find my top level code below. 'Start' signal is to be controlling the initiation of other processes. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; use IEEE.MATH_REAL.ALL; ----------------------------------------------------- entity top_module is port( --------------------UART_GUI------------------------------- RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); ---COMMON INPUTS--- clk, rst : in std_logic; --send_ccd : in std_logic;---------------CCD control SH,ICG,master_ccd_clock : out std_logic; ----FOR AD7980-------- --sample: in std_logic; -------------- to start sampling samp_ind: out std_logic;---------------indicates sampling in process adc_cnv : out std_logic;---------------cnv for AD7980 adc_clk : inout std_logic;--------------SPI clock adc_miso : in std_logic;------------------output from AD7980 -------FIFO SIGNALS-------- WriteEn , ReadEn : in std_logic; -------------fifo controls full, empty : out std_logic ------------------indicates fifo status ); end top_module; architecture structural of top_module is ----------------------------------------------------------------------------UART CONTROL GUI------------------------------------- component receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END component receiver; ----------------------------------------FIFO COMPONENT DECLARATION ----------------------------------------------------------------- component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; -------------------------------------------------------------------------------------------------------------------------- signal fifo_data_out : STD_LOGIC_VECTOR (15 downto 0); signal adc_out : std_logic_vector(15 downto 0); signal start :std_logic; -------------------------UART_RX_FOR CONTROL_ OF_PROCESSES--------------------------------------------------------------- process(Clk,RxData) begin if RxData = "01110011" then start <= '1' ; elsif RxData = "01110000" then start <= '0'; else start <= '0'; end if; end process; --------------------AD7980PORTMAP---------------------------------------------------------------------------------- AD7980 : entity work.AD7980 port map ( clock => clk, sample => start, -- data output Dout => adc_out(15 downto 0), samp_ind => samp_ind, -- ADC connection adc_miso => adc_miso, adc_cnv => adc_cnv, adc_clk =>adc_clk ); ---------------------------------------------FIFO PORTMAP---------------------------------------------------------------- fifo_i: component fifo port map ( clk_100MHz => clk, din_0(15 downto 0) => adc_out(15 downto 0), dout_0(15 downto 0) => fifo_data_out(15 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); ccd_control : entity work.TCD1103GFG port map ( clock => clk, send => start, SH => SH, ICG => ICG, master_ccd_clock => master_ccd_clock); ---------------------------------------------------------------UART GUI CONTROL--------------------------------------- uart_gui : entity work.receiver port map ( clk => clk, reset => rst, RxD => RxD, RxData => RxData ); end structural; Here is the UART receiver open source code I'm using that works LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY receiver IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; RxD : IN STD_LOGIC; RxData : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END receiver; ARCHITECTURE behavioural OF receiver IS SIGNAL shift : STD_LOGIC; SIGNAL state : STD_LOGIC; SIGNAL nextstate : STD_LOGIC; SIGNAL bitcounter : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL samplecounter : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL counter : STD_LOGIC_VECTOR(13 DOWNTO 0); SIGNAL rxshiftreg : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL clear_bitcounter : STD_LOGIC; SIGNAL inc_bitcounter : STD_LOGIC; SIGNAL inc_samplecounter : STD_LOGIC; SIGNAL clear_samplecounter : STD_LOGIC; constant clk_freq: integer := 100000000; constant baud_rate :integer := 9600; constant div_sample :integer := 4; constant div_counter :integer := (clk_freq/(baud_rate*div_sample)); constant mid_sample : integer := (div_sample/2); constant div_bit : integer := 10; BEGIN RxData <= rxshiftreg(8 DOWNTO 1); PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN state <= '0'; bitcounter <= "0000"; counter <= "00000000000000"; samplecounter <= "00"; ELSE counter <= counter + "00000000000001"; if (counter>= div_counter - 1) then counter <= "00000000000000"; state <= nextstate; IF (shift = '1') THEN rxshiftreg <= (RxD & rxshiftreg(9 DOWNTO 1)); END IF; IF (clear_samplecounter = '1') THEN samplecounter <= "00"; END IF; IF (inc_samplecounter = '1') THEN samplecounter <= samplecounter + "01"; END IF; IF (clear_bitcounter = '1') THEN bitcounter <= "0000"; END IF; IF (inc_bitcounter = '1') THEN bitcounter <= bitcounter + "0001"; END IF; END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN shift <= '0'; clear_samplecounter <= '0'; inc_samplecounter <= '0'; clear_bitcounter <= '0'; inc_bitcounter <= '0'; nextstate <= '0'; CASE state IS WHEN '0' => IF (RxD = '1') THEN nextstate <= '0'; ELSE nextstate <= '1'; clear_bitcounter <= '1'; clear_samplecounter <= '1'; END IF; WHEN '1' => nextstate <= '1'; IF (samplecounter = (mid_sample - 1)) THEN shift <= '1'; END IF; IF (samplecounter = (div_sample - 1)) THEN IF (bitcounter = (div_bit - 1)) THEN nextstate <= '0'; END IF; inc_bitcounter <= '1'; clear_samplecounter <= '1'; ELSE inc_samplecounter <= '1'; END IF; WHEN OTHERS => nextstate <= '0'; END CASE; END IF; END PROCESS; end behavioural; I'm unsure if the issue is because of the number of clock cycles for which the character 's' exists. Please help me understand the miss here.
  2. rmd91

    Zybo-Z7 Serial Port not working

    Hello, I've been to set up a new Zybo board but I'm stuck with a serial port issue. I built my design with the provided board files in Vivado 2017.4. I tried a simple "hello world" in SDK but only got a bunch of unprintable characters. I have Tera Term set up for 115200, 8-bit, 1 stop, no parity. I tried Putty as well and had the same results. I verified the Vivado project is using UART1 MIO48..49. I intermittently can get the correct initialization message from the preloaded QSPI image, but most times it's unprintable characters. I also tried the pre-built Linux from the 2017.4 Zybo Petalinux BSP with the same result. It's definitely booting, but the terminal output is unprintable characters. Other things to note: * I'm running off USB power. I'm plugged directly into my laptop * Sometimes pressing the Reset button makes the PGOOD LED flicker until power cycled Thank you Richard
  3. Hi, I have designed an UART core without any flow control for use with FPGA devices when communicating with LabVIEW. I am looking for a way to receive (from FPGA to LabVIEW) data fast and correctly, hence I am investigating the following configurations for setting the VISA READ when to start or stop reading UART bytes: 1-with termination char: this is very tricky in the binary world as are the FPGAs, because it can trigger false stops sooner than expected. A solution will be to use a custom 3 termination chars like "/n/n/n" and LabVIEW will read till will receive this sequence. 2- by counting the received bytes and compare them with the expected number of bytes and the process the data. 3- using flow control. Which approach is better to be used? Or do you have another ideas? Thanks, V.M.
  4. Archana Narayanan

    MCP3008 Interfaced with basys 3 using SPI

    Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf
  5. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from After installing as described in I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  6. Hello, I am new to ZYBO board. I am working on a project where I want to control a sensor from my ZYBO board using UART and receive the data from the sensor via SPI. I searched for the reference design, tutorials online to get started with, but I could not find any. Can anyone point me in the right direction where I can refer to and implement my work? THANK YOU. This is my aim as shown below. I want Zybo to be the main host, not my PC.
  7. Antonio Daril Crispino

    UART communication control with CMOD A7

    Hi everybody, I have to communicate with the FPGA on my CMOD A7 board through the on board FTDI FT2232HQ chip. While on a PmodUSBUARD, for example, I can use the RTS/CTS hardware wires for the flow control, on the board datasheets it's written that I can only use the TX and RX hardware wires and that there are no RTS/CTS wires (fact confirmed by the board .xdc file too). How can I set reliable control flow for my high-speed communication (from 6Mbaud to 12Mbaud) ? Any advice? Thank you in advance, Antonio Daril Crispino
  8. mcamacho

    PART NUMBER OF J10 usb uart port Arty-7

    Hello everyone. I need to know the part number of the J10 USB UART connector integrated in ARTY-7 board. Best regards.
  9. John1123


    Hi, I don't really know where to post this but I have a question. I am very new to FPGAs so this may seem as a very stupid question. i wanted to use my ARTY and read values from the analog IO and output the values through UART. I am familiar with setting up UART and microblaze but I have no idea how to use the analog IO. Any help will be kindly appreciated.
  10. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx
  11. Hi ! I am interested in using the Digital Discovery controlling multiple devices at the same time with different protocols. E.g. I would like to setup the UART on the digital discovery on DIO 28 as TX and 29 as RX while using SPI at the same time on the default setup DIOs as 24/CS, 25/CLK, 26/DQ0/MOSI, 27/DQ1/MISO. Using then I2C on e.g. 31/SCL and 30/SDA and CAN on 36/RX and 37/TX on top of that would be very nice as well. Is this possible from the user interface (which I would prefer) or do I need to create custom code for that?
  12. MVS

    Arty Z7-20 Serial Com

    Hello everyone, I bought an Arty z7-20 board a month ago and my first project depends on serial communication. I made a program in VHDL but I could not know which are the pins that I should assign to the uart. From schematic file, i understand that i have to comunicate the fpga with the pins C5 and C8, for Tx and Rx, on the chip bank500, but.... i dont see what are the pins to enable uart in the .xdc master file to do this. A lot of thanks for share your experience! I leave here a simple design to taste the uart. The idea is that the fpga recive a data and send it back to a terminal. SERIAL_ENSAYO.vhd
  13. hello, I practice to use vivado 2018.2 to create two AXI GPIOs like the first picture. I could use C program to pass the ON/OFF from switchs to leds;however, the XGpio_DiscreteRead() is always blocked by gets() when i want to use gets() to get cmd,and write data to leds according cmd. The following is my C code.Please introduce me to solve the problem. Thank you a lot. #include "xparameters.h" #include "xgpio.h" #include <stdio.h> #include <stdlib.h> #include "sleep.h" int main(){ XGpio output,input; /* SW &LED Instance */ int button_data=0x00; int switch_data=0; int led_value = 0; int i=0; char cmd[4]; XGpio_Initialize(&output, XPAR_AXI_GPIO_1_DEVICE_ID); XGpio_SetDataDirection(&output, 1, 0x0); XGpio_Initialize(&input, XPAR_AXI_GPIO_0_DEVICE_ID); XGpio_SetDataDirection(&input, 1, 0xF); while(1) { i++; printf("This the %d time run the while loop\n\r",i); printf("Enter Command: \n\r"); gets(cmd); switch_data = XGpio_DiscreteRead(&input, 1); printf("switch_data = %d\n\r",switch_data); led_value = switch_data+1; XGpio_DiscreteWrite(&output, 1, led_value); printf("data wrtie over"); printf("=========================================="); usleep(20000); } return 0; }
  14. Vonmuller

    Custom Function Generator

    This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  15. K_Ashish

    UART Interrupt in zybo queries

    Hello, I am trying to use UART in interrupt mode using zybo board. I tried Hello World example using UART1 of PS which is 48 49 MIO and it is working. I referred interrupt example in ~\Xilinx\SDK\2016.2\data\embeddedsw\XilinxProcessorIPLib\drivers\uartps_v3_1\examples. But I am not connect uart with Interrupt controller or GIC. Any suggestion on designing hardware in vivado and which reference code to use?
  16. bri

    nexys 4 ddr UART

    What is max baud rate of UART on Nexsys4 DDR board? Datasheet for FT2232H indicates slower speeds when using RS232. I looked on schematics for Nexsys4 DDR and don't see part so couldn't check how it is actually wired up. Also trying to understand end-end application to FPGA connections in terms of flow control. Trying to bring data into board through RS485 PMOD that I can't flow control so thought I might be able to use FPGA to manage flow control and output data out of UART to host PC and store to file. Trying to understand max data rates, how much buffering I need in FPGA, etc. Not sure if processor running software on FPGA would be better or just implement in hardware.
  17. Dear all, I'm trying to integrate Pmod GPS on my Xilinx ZCU102 platform with a Linux OS. To do so, I'm using the resources available in Digilentinc's vivado-library zip (PmodGPS_v1_1 IP + software drivers using xuartns550). I managed to make it work correctly in polling mode (calling GPS_getData func) with a clock freq of 49.995 MHz and a baudrate of 9600 symbols/s. Nonetheless, when I try to increase the baudrate to 115200, the NMEA messages in the ->recv buffer get corrupted. For instance, some messages are not correctly formatted because one comma has been flipped to another char and it makes the GPS_formatSentence function to seg fault. It's really important for my project to achieve higher rates (I'm working on a 60 fps camera and I would like to associate a GPS data to each frame and can not afford to spend too much time in the GPS_getData function in I want to preserve real time operation). Here are the hypothesis I make on the cause of this problem: a) The clock at both ends of the UART link are not synchronized. As far as I understand, this problem can also occur at low baud rates so it's probably not the main cause (cf PercentError computed in XUartNs550_SetBaudRate). b ) There is corruption on the physical link (my PMOD in connected to the ZCU102 using female-female jumper wires). Here are the workaround I tried so far: a) Check the checksum of the NMEA message before calling GPS_formatSentence and discard corrupted messages. This improve the reliability of the system but some problems still appear from time to time which is definitely not acceptable. I feel like it will be quite complex to design a check that is able to handle any kind of corruption (what if a $ sign or a * gets corrupted ?) b ) Use baud rate = 9600 and call GPS_getData and GPS_formatSentence in another thread (so that the main thread is not waiting for GPS_getData to complete). Unfortunately, I only have little experience in multi-threaded programming and I did not manage to make it work properly. I also think it's not very good practice, it would be better to make it work at higher baud rates. Do you have any complementary idea about how to fix that ? Thanks in advance, Alexandre
  18. Hello, So I am trying to write a script that will be taking advantage of both output and both inputs to the AD2 as well as take select information and send it out to two (for now) serial lines. I have written a script to control everything I need minus the actual setup of the UART settings, sending the data over the Tx line and receiving over the Rx line. Are there any examples of how to send the data over script as opposed to using the built-in GUI of Waveforms? Thanks, Ryne
  19. Brooklynoutlier

    Problem with UART, Arty S750 to Windows 7 SP 1

    Anyone else experienced a problem with communicating to an HP laptop running Windows 7 SP 1 from an Arty S7 50 through the UART port? I boiled the application down to just two simple modules, but I still get an extra character (x"FF") added to every character sent from the board to the laptop. In other words, trying to send "01234" from the board results in "0ÿ1ÿ2ÿ3ÿ4ÿ" being received (ÿ has ascii value xFF). I've tried reinstalling drivers using files from the FTDI site, and tested with two different terminal programs (PuTTY and Termite), but the result is always the same. Communication in the other direction works just fine.
  20. Hello I am a user of Analog Discovery2 and I believe it is missing one very important (for me at leas) function. I basically want to monitor and register the communication between two devices which use UART to do so. The Protocol panel looks great but I am able to register only one of the devices at the same time. Logic panel is very unfeasible in my case because I want to register many lines of the communication (like 5 min). Is there any way I can achieve that? Maybe there is a custom script which would help in my case?
  21. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  22. Hi, I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP. The AXI Uartlite is configured as follows. CLK 1MHz, baud rate 9600, data bits 8 S_AXI_wvalid <= '1'; S_AXI_wstrb <= '1'; S_AXI_awvalid <= '1'; S_AXI_aresetn <= '1'; S_AXI_awaddr <= "0100"; S_AXI_wdata <= "00000000000000000000000001010011"; When I simulate, the TX port output of AXI Uartlite just remains ‘X’ state instead toggling as per S_AXI_wdata. I have simulated upto 4 seconds and ll the values are initialized from the beginning of simulation. Am I missing any configuration setting? or anything needs to be carried out to get teh data at TX port ? Help is much appreciated. Regards, Subash
  23. Weevil

    32bit data transfer using uartlite

    Hi all, actual i try to transfer a data stream from the DMA via uart to my PC. In my design an DDS-compiler generates a 32bit sine wave, which should be transfered via uart and read by a python script. The general data transfer works, but sometimes i get some noisy signal. This signal happens also when using a lower sample rate. For the uart data transfer actual i did not add any marker where the 32 bit value begins or ends. So i expect this is the problem, but i don't know how to include this in my SDK and python code. Maybe any suggestion? (The FPGA design is similar to my previous post using the Cmod A7) Plot of the result with pyqtgraph: SDK code: int XAxiDma_Poll_Uart(u16 DeviceId) { int Status, Index; int Tries = NUMBER_OF_TRANSFERS; u32 *RxBufferPtr; u32 *RxPacket; u8 BytesSent; RxBufferPtr = (u32 *) RX_BUFFER_BASE; RxPacket = (u32 *) RX_BUFFER_BASE; for (Index = 0; Index < MAX_PKT_LEN_WORDS; Index ++) { RxBufferPtr[Index] = 0xCC; } /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache is enabled*/ Xil_DCacheFlushRange((u32)RxBufferPtr, MAX_PKT_LEN); Status = XAxiDma_SimpleTransfer(&AxiDma, (u32) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); if (Status != XST_SUCCESS) {return XST_FAILURE;} while (XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)) {/* Wait*/} /* Invalidate the TestBuffer before receiving the data, in case the Data Cache is enabled*/ Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN); //send data to uart BytesSent = XUartLite_Send(&UartLite, RX_BUFFER_BASE, sizeof(RxPacket)); while (XUartLite_IsSending(&UartLite)) {/*Wait*/} return XST_SUCCESS; } Python code: import numpy as np import sys import serial buffersize = 512 byte_number = 4 ser = serial.Serial( port='COM6',\ baudrate=921600,\ parity=serial.PARITY_NONE,\ stopbits=serial.STOPBITS_ONE,\ bytesize=serial.EIGHTBITS,\ timeout=0) for u in range(20): #read serial buffer s = #convert to integer for i in range (int(len(s)/byte_number)): res_value = dataSerial[(i*byte_number):((i+1)*byte_number)] value = int.from_bytes(res_value, byteorder='little', signed = True) dataSerialFormated = np.append(dataSerialFormated, value)
  24. Hi folks! I'm thinking of buying an Analog Discovery 2. One piece of functionality I need is sniffing a serial connection between two devices. Not just a set number of samples - I mean capturing both TX and RX bytes to file/PC memory, for however many hours I need to catch my nasty little bug. The actual amount of data transfered is low. I'm actually utilizing maybe 30% of the capacity, at around 10kB/s TX and RX. On top of that, I'd like to add support for my custom software protocol that's running on the UART. Kind of like in wireshark you can see what a packet is, not just a plaintext context-less byte barf. If waveforms doesn't support this, I'm completely fine with writing an utility that, say, takes raw UART data over loopback TCP and formats it externally. Is this possible on the Analog DIscovery? What settings should I be using to make it work like that?
  25. John_Anacall

    Questions about how to use UART

    Once again I'm sorry if I'm asking what can be considered silly questions, but I'm diving into the FPGA world by myself and I'm having serious dificulties finding documentation or examples that fit my questions. I'm using a Cmod A7 and I want to develop a GUI to let the user define some parameters. Through what I've been researching I believe the way to do it is using UART with the micro usb of the board. I've seen some examples of UART implementations, some I found in responses here on the forum, but due to my lack of knowledge it seems to me they lack important things so I could understand them. So I'll ask two questions: 1 - I believe that if I want to let the user change some parameter, that parameter must be a register and I need to know its adress. But how do I define the adress of that register? I haven't been able to find any example for this. 2 - It seems that the Cmod A7 has two UART ports according to the XDC file, so exactly how am I supposed to use them? Will that make a diference from examples like this one? João