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Found 50 results

  1. Hi folks! I'm thinking of buying an Analog Discovery 2. One piece of functionality I need is sniffing a serial connection between two devices. Not just a set number of samples - I mean capturing both TX and RX bytes to file/PC memory, for however many hours I need to catch my nasty little bug. The actual amount of data transfered is low. I'm actually utilizing maybe 30% of the capacity, at around 10kB/s TX and RX. On top of that, I'd like to add support for my custom software protocol that's running on the UART. Kind of like in wireshark you can see what a packet is, not just a plaintext context-less byte barf. If waveforms doesn't support this, I'm completely fine with writing an utility that, say, takes raw UART data over loopback TCP and formats it externally. Is this possible on the Analog DIscovery? What settings should I be using to make it work like that?
  2. Questions about how to use UART

    Once again I'm sorry if I'm asking what can be considered silly questions, but I'm diving into the FPGA world by myself and I'm having serious dificulties finding documentation or examples that fit my questions. I'm using a Cmod A7 and I want to develop a GUI to let the user define some parameters. Through what I've been researching I believe the way to do it is using UART with the micro usb of the board. I've seen some examples of UART implementations, some I found in responses here on the forum, but due to my lack of knowledge it seems to me they lack important things so I could understand them. So I'll ask two questions: 1 - I believe that if I want to let the user change some parameter, that parameter must be a register and I need to know its adress. But how do I define the adress of that register? I haven't been able to find any example for this. 2 - It seems that the Cmod A7 has two UART ports according to the XDC file, so exactly how am I supposed to use them? Will that make a diference from examples like this one? João
  3. cannot connecto to terminal on Zybo Z7

    Hello, just plugged in my new Zybo Z7 471-015 but cannot connect to serial port. It works on the Zybo. PROG UART is connected to USB PC BSP stdin, stdout is set to ps7_uart_1 I have no other application open that is accessing the serial ports to make sure I dis- and reconnected the Zybo Z7, still doesn't appear on the port list Zybo Z7 appears as USB Serial Converter A and B in the device mngr restarted PC tried another USB port replaced USB cable, both are data cables JP6 is set to USB JP5 is set to JTAG drivers had been installed with Vivado 2017.2 re-installed Vivado 2017.2 cable drivers, restarted PC USB port should be listed even without any PL configuration loaded, right?
  4. Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dds-compiler over the Stream-Data-FIFO to the FFT right?
  5. Hi, I want to understand the main difference when programming a board which is configured using a BSP (Ex: ZYBO) and which is configured using only device details(Ex: xc7z010clg400-1). I'm asking because I'm configuring only zynq in the block design with uart1 for hello world application. If I program using ZYBO bsp it works but not if I use only the device details. I need to understand this since my actual project is on a custom z7010 board and not a regular development board and I'm not able to get the uart up and running. I wanted to figure it out on a development board as it is easier to understand. I think it is some simple settings detail that I'm missing. Appreciate any help.
  6. uart receiving module for 16 or more bits

    Good morning everyone, I am currently developing a computer application in Matlab with help of VHDL and the Nexys 4 DDR, my problem is that I need to send a vector of 16 or more bits through an aurt module, the aurt module only sends 8 bits but I need to send more bits. anyone have any idea how to receive more than 8 bits per aurt? , I know that you should make the matrix reception module in vhdl and I was trying with this module that I have, but it does not work, and I have no idea how to do it to receive matrix. thanks. recepción.txt
  7. Hi, While there are many examples showing a basic Hello World using a Zynq UART, how do we read in data from the console using the same UART? Can anyone please guide me to the right example. I cudn't find one.
  8. motor controller with BASYS3 and UART

    Hi everyone, I am working on a project about drone. The project is sending and receiving data through UART and controlling the four brushless servo motors by getting these value for the speed of servo motors. I could find and combine codes for accomplishing the communication between fpga and the computer. However, I cannot make a relationship between coming data with servo motor. I get the coming UART data one by one by converting integer for duty cycle. Could you help me out this, how can I get the received data and send it to servo motors? Thanks in advance.
  9. UART and XADC

    Good morning, I am currently developing a graphical interface that allows visualizing the XADC data of the NEXYS 4 DDR, I found the problem that the UART communication protocol sends 8 bits as information, the xadc samples to 12 bits, someone knows some idea, solution or module that allows me to send the 12 bits of xadc by uart? Thank you
  10. Hello. I have to adjust the speed (baud), parity bit (if I want), stop bit. For both software alike. I would like to know if anyone has that code in VHDL / VERILOG ? (UART/JTAG)
  11. UART communication protocol in nexys 4 DDR for XADC

    Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  12. Protocol

    Hi, In the Protocol tool, the UART tab The ´Receive to File´ and ´Save´ button generate a windows error by me. Thanks in advance, Hans
  13. Arty Z7-20 hello world / BSP regeneration

    I'm trying to get the Arty Z7-20 board to simply print "hello world" to the SDK terminal. I have the board files installed from GitHub. I made a vivado project with the Zynq PS and a few random IPs. The PS is configured to use UART0 (mio pins 14/15). When I run the hello world example in the SDK, I don't get anything on the COM port and the TX/RX LEDs don't light up. There are 2 COM ports that SDK detects (3 and 4). If I try to connect to 3 it says it's already connected. I'm assuming this is the because it uses COM3 for downloading the program. So I connect to COM4 @ 115200. Any ideas on how to debug this issue? Thanks EDIT: I was able to get it working---the issue was resolved by deleting and regenerating the BSP in SDK. I've never had to do this before as SDK has done all of the regenerating automatically. Can someone explain a bit why/when it is necessary to regenerate the BSP?
  14. Hello, I would like to know if the PL in Zybo boards can be used for a HDL FPGA design without the Zynq PS (no software). Is there some reference/demo/example about this case? Particularly, I want to know how to connect the USB-UART port to a custom HDL (UART) Module in the PL section, but using the same pins (i.e. MIO48, MIO49) that Zynq normally uses. Thanks in advance
  15. Nexys 4 DDR shows up with two COM ports

    We use Nexys 4 DDR boards for testing our platform. While with most of the Windows host PCs there are no issues, with one of our clients' when the board is plugged in (using the supplied micro USB cable) it shows up as two COM ports under Windows's Device Manager. We suspect this is behind that we can't properly run Xilinx SDK programs on the board, the debugger looses the connection. Is it normal that the board shows up as two COM ports? (When the board is de-attached the ports disappear, so both are surely the single board.) If yes, can this cause issues? If now, how can we begin to troubleshoot the problem, what can possible be behind it? Thank you in advance!
  16. UART interrupt example

    Hello everyone! I am facing a problem while working with a project on Zybo. I have UART1 input (the input connected with microUSB port) enabled in my project and I want to make a simple user interface in a standalone application. I have already found several examples of such applications but the thing is that I don't want the program to continuously examine the input - I want the processor to get an interrupt every time the user makes an input. Is there any example of how this has to be done? Thank you in advance.
  17. Hello everybody! I just finished a series of posts on zipcpu.com describing how a debugging access can be created out of the serial port to provide access into the internals of an FPGA. Examples include how you can read or write FPGA block RAM, or even an internal scope. Today's post described how to build a software facility for accessing memory mapped I/O components within your design. Hence, you can issue read and write commands from your host PC software to access the internals of your design. In many ways, this design was motivated by requests on the forum asking for help while trying to debug an FFT (as one example). It's a similar, albeit simpler, debugging component to the one I've used myself for debugging designs. Indeed, I've used the concept presented to debug flash controllers, block RAM, wishbone bus components, the ZipCPU, the ICAPE configuration interface, and much more. In addition to the articles on zipcpu.com, you can also find all of the code posted on GitHub and licensed under LGPL--should you wish to try it out yourself, or even modify it for your own design. Even better, since the design is built of entirely open source components, you can build a Verilator simulation and simulate your entire design, a capability many students have struggled to do with their designs. Not only that, you can also integrate your own components into the design, while continuing to simulate all of the logic within the design. Dan
  18. Intercept UART

    Can I intercept UART signal ... ? what I need to do is to recieve an UART on Analog Discovery2 and pass the signal directly to the pattern generator in real time
  19. UART triggering

    Hi, In the attached picture i try to trigger in 2 way's 1. Protocol on value: h48[H] 2. Direct on the Falling edge Both ways don't work the system randomly triggers on what? Thanks in advance, Hans.
  20. UART Interrupt in zybo queries

    Hello, I am trying to use UART in interrupt mode using zybo board. I tried Hello World example using UART1 of PS which is 48 49 MIO and it is working. I referred interrupt example in ~\Xilinx\SDK\2016.2\data\embeddedsw\XilinxProcessorIPLib\drivers\uartps_v3_1\examples. But I am not connect uart with Interrupt controller or GIC. Any suggestion on designing hardware in vivado and which reference code to use?
  21. In my project, I need to use the UART ports on the NexysVideo board to transmit signals to a Raspberry. I defined 2 signals Rx_raspi as an in std_logic and Tx_raspi as an out std_logic, and in the XDC file, they are defined as: set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports Rx_raspi ]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports Tx_raspi ]; while implementing, errors show that no ports matched. [Vivado 12-584] No ports matched 'Tx_raspi'. [Vivado 12-584] No ports matched 'Rx_raspi'. [Common 17-55] 'set_property' expects at least one object. [Common 17-55] 'set_property' expects at least one object. What was wrong?
  22. SDK Coding

    Its been a few months since I've been introduced to FPGA design and have successfully completed some basic projects, however, while trying to effectively establish communication with devices via protocols such as uart, spi, and i2c I usually fall short. From what I understand you must enable these through the ZYNQ7 processor on block design or drop in their respective IP blocks. How to actually connect these to external devices becomes fuzzy for me and interpreting/modifying the SDK code is very difficult. In short I'm looking for some help/resources to get the ball rolling on these type of projects, and how to actually understand/develop the C code for processor myself, on both the Microzed and Zybo development boards. Thank you
  23. Within the schematics of the NEXYS 4 and NEXYS VIDEO boards I couldn't find the part with the Micro-USB JTAG bridge. The part with the FT2232HQ chip is left out in both schematics. Is there a reason for neglecting those parts? Could I find the schematics elsewhere? I'm especially interested in the differences between a combined JTAG and UART Micro-USB solution (as seen on NEXYS 4) and two separate solutions Micro-USB JTAG (1) and Micro-USB UART (2) (as seen on NEXYS VIDEO).
  24. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h> #include "ap_cint.h" int PRBS_prj(int bit) { #pragma HLS INTERFACE s_axilite port=return bundle=a int start_state = 0xCD; int lfsr = start_state; unsigned period = 0; do { /* taps: 3, 2 and 1 ; feedback polynomial: x^3 + x^2 + 1 */ bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1; printf("%d", bit); lfsr = (lfsr >> 1) | (bit << 7); ++period; } while (lfsr != start_state); return bit; } or int main(void) { static int lfsr = 0x3425u; unsigned int mask = 0xF0; int bit; /* Must be 16bit to allow bit<<15 later in the code */ //taps: 16 14 13 11; feedback polynomial: x^16 + x^14 + x^13 + x^11 + 1 bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5) ) & 1; lfsr = (lfsr >> 1) | (bit << 15); for (mask = 0xF0; mask; mask >>= 1) putchar('0' + !!(lfsr & mask)); return lfsr; }
  25. UART1 in Zybo zynq-7000

    I want to use a uart protocol to send quadrature signals from a rotary encoder, using the j11 USB/UART-JTAG connector on a Zybo Zynq7000. Would like to read signals to SDK terminal initially. I am unsure where I would connect the "QEA" and "QEB" signals from the encoder. Additionally in the vivado block design i am uncertain if I would need to use the AXI UART or if this can be done solely through the zynq process. Consequently I do not know where to start with SDK code that would be necessary to implement such a design. Fairly new to FPGA design so specifics would be great great but tutorials/reference material are enthusiatically accepted