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Found 45 results

  1. uart receiving module for 16 or more bits

    Good morning everyone, I am currently developing a computer application in Matlab with help of VHDL and the Nexys 4 DDR, my problem is that I need to send a vector of 16 or more bits through an aurt module, the aurt module only sends 8 bits but I need to send more bits. anyone have any idea how to receive more than 8 bits per aurt? , I know that you should make the matrix reception module in vhdl and I was trying with this module that I have, but it does not work, and I have no idea how to do it to receive matrix. thanks. recepción.txt
  2. Hi, While there are many examples showing a basic Hello World using a Zynq UART, how do we read in data from the console using the same UART? Can anyone please guide me to the right example. I cudn't find one.
  3. motor controller with BASYS3 and UART

    Hi everyone, I am working on a project about drone. The project is sending and receiving data through UART and controlling the four brushless servo motors by getting these value for the speed of servo motors. I could find and combine codes for accomplishing the communication between fpga and the computer. However, I cannot make a relationship between coming data with servo motor. I get the coming UART data one by one by converting integer for duty cycle. Could you help me out this, how can I get the received data and send it to servo motors? Thanks in advance.
  4. UART and XADC

    Good morning, I am currently developing a graphical interface that allows visualizing the XADC data of the NEXYS 4 DDR, I found the problem that the UART communication protocol sends 8 bits as information, the xadc samples to 12 bits, someone knows some idea, solution or module that allows me to send the 12 bits of xadc by uart? Thank you
  5. Hello. I have to adjust the speed (baud), parity bit (if I want), stop bit. For both software alike. I would like to know if anyone has that code in VHDL / VERILOG ? (UART/JTAG)
  6. UART communication protocol in nexys 4 DDR for XADC

    Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  7. Protocol

    Hi, In the Protocol tool, the UART tab The ´Receive to File´ and ´Save´ button generate a windows error by me. Thanks in advance, Hans
  8. Arty Z7-20 hello world / BSP regeneration

    I'm trying to get the Arty Z7-20 board to simply print "hello world" to the SDK terminal. I have the board files installed from GitHub. I made a vivado project with the Zynq PS and a few random IPs. The PS is configured to use UART0 (mio pins 14/15). When I run the hello world example in the SDK, I don't get anything on the COM port and the TX/RX LEDs don't light up. There are 2 COM ports that SDK detects (3 and 4). If I try to connect to 3 it says it's already connected. I'm assuming this is the because it uses COM3 for downloading the program. So I connect to COM4 @ 115200. Any ideas on how to debug this issue? Thanks EDIT: I was able to get it working---the issue was resolved by deleting and regenerating the BSP in SDK. I've never had to do this before as SDK has done all of the regenerating automatically. Can someone explain a bit why/when it is necessary to regenerate the BSP?
  9. Hello, I would like to know if the PL in Zybo boards can be used for a HDL FPGA design without the Zynq PS (no software). Is there some reference/demo/example about this case? Particularly, I want to know how to connect the USB-UART port to a custom HDL (UART) Module in the PL section, but using the same pins (i.e. MIO48, MIO49) that Zynq normally uses. Thanks in advance
  10. Nexys 4 DDR shows up with two COM ports

    We use Nexys 4 DDR boards for testing our platform. While with most of the Windows host PCs there are no issues, with one of our clients' when the board is plugged in (using the supplied micro USB cable) it shows up as two COM ports under Windows's Device Manager. We suspect this is behind that we can't properly run Xilinx SDK programs on the board, the debugger looses the connection. Is it normal that the board shows up as two COM ports? (When the board is de-attached the ports disappear, so both are surely the single board.) If yes, can this cause issues? If now, how can we begin to troubleshoot the problem, what can possible be behind it? Thank you in advance!
  11. UART1 in Zybo zynq-7000

    I want to use a uart protocol to send quadrature signals from a rotary encoder, using the j11 USB/UART-JTAG connector on a Zybo Zynq7000. Would like to read signals to SDK terminal initially. I am unsure where I would connect the "QEA" and "QEB" signals from the encoder. Additionally in the vivado block design i am uncertain if I would need to use the AXI UART or if this can be done solely through the zynq process. Consequently I do not know where to start with SDK code that would be necessary to implement such a design. Fairly new to FPGA design so specifics would be great great but tutorials/reference material are enthusiatically accepted
  12. UART interrupt example

    Hello everyone! I am facing a problem while working with a project on Zybo. I have UART1 input (the input connected with microUSB port) enabled in my project and I want to make a simple user interface in a standalone application. I have already found several examples of such applications but the thing is that I don't want the program to continuously examine the input - I want the processor to get an interrupt every time the user makes an input. Is there any example of how this has to be done? Thank you in advance.
  13. Hello everybody! I just finished a series of posts on zipcpu.com describing how a debugging access can be created out of the serial port to provide access into the internals of an FPGA. Examples include how you can read or write FPGA block RAM, or even an internal scope. Today's post described how to build a software facility for accessing memory mapped I/O components within your design. Hence, you can issue read and write commands from your host PC software to access the internals of your design. In many ways, this design was motivated by requests on the forum asking for help while trying to debug an FFT (as one example). It's a similar, albeit simpler, debugging component to the one I've used myself for debugging designs. Indeed, I've used the concept presented to debug flash controllers, block RAM, wishbone bus components, the ZipCPU, the ICAPE configuration interface, and much more. In addition to the articles on zipcpu.com, you can also find all of the code posted on GitHub and licensed under LGPL--should you wish to try it out yourself, or even modify it for your own design. Even better, since the design is built of entirely open source components, you can build a Verilator simulation and simulate your entire design, a capability many students have struggled to do with their designs. Not only that, you can also integrate your own components into the design, while continuing to simulate all of the logic within the design. Dan
  14. Intercept UART

    Can I intercept UART signal ... ? what I need to do is to recieve an UART on Analog Discovery2 and pass the signal directly to the pattern generator in real time
  15. UART Interrupt in zybo queries

    Hello, I am trying to use UART in interrupt mode using zybo board. I tried Hello World example using UART1 of PS which is 48 49 MIO and it is working. I referred interrupt example in ~\Xilinx\SDK\2016.2\data\embeddedsw\XilinxProcessorIPLib\drivers\uartps_v3_1\examples. But I am not connect uart with Interrupt controller or GIC. Any suggestion on designing hardware in vivado and which reference code to use?
  16. UART triggering

    Hi, In the attached picture i try to trigger in 2 way's 1. Protocol on value: h48[H] 2. Direct on the Falling edge Both ways don't work the system randomly triggers on what? Thanks in advance, Hans.
  17. In my project, I need to use the UART ports on the NexysVideo board to transmit signals to a Raspberry. I defined 2 signals Rx_raspi as an in std_logic and Tx_raspi as an out std_logic, and in the XDC file, they are defined as: set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports Rx_raspi ]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports Tx_raspi ]; while implementing, errors show that no ports matched. [Vivado 12-584] No ports matched 'Tx_raspi'. [Vivado 12-584] No ports matched 'Rx_raspi'. [Common 17-55] 'set_property' expects at least one object. [Common 17-55] 'set_property' expects at least one object. What was wrong?
  18. SDK Coding

    Its been a few months since I've been introduced to FPGA design and have successfully completed some basic projects, however, while trying to effectively establish communication with devices via protocols such as uart, spi, and i2c I usually fall short. From what I understand you must enable these through the ZYNQ7 processor on block design or drop in their respective IP blocks. How to actually connect these to external devices becomes fuzzy for me and interpreting/modifying the SDK code is very difficult. In short I'm looking for some help/resources to get the ball rolling on these type of projects, and how to actually understand/develop the C code for processor myself, on both the Microzed and Zybo development boards. Thank you
  19. Within the schematics of the NEXYS 4 and NEXYS VIDEO boards I couldn't find the part with the Micro-USB JTAG bridge. The part with the FT2232HQ chip is left out in both schematics. Is there a reason for neglecting those parts? Could I find the schematics elsewhere? I'm especially interested in the differences between a combined JTAG and UART Micro-USB solution (as seen on NEXYS 4) and two separate solutions Micro-USB JTAG (1) and Micro-USB UART (2) (as seen on NEXYS VIDEO).
  20. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h> #include "ap_cint.h" int PRBS_prj(int bit) { #pragma HLS INTERFACE s_axilite port=return bundle=a int start_state = 0xCD; int lfsr = start_state; unsigned period = 0; do { /* taps: 3, 2 and 1 ; feedback polynomial: x^3 + x^2 + 1 */ bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1; printf("%d", bit); lfsr = (lfsr >> 1) | (bit << 7); ++period; } while (lfsr != start_state); return bit; } or int main(void) { static int lfsr = 0x3425u; unsigned int mask = 0xF0; int bit; /* Must be 16bit to allow bit<<15 later in the code */ //taps: 16 14 13 11; feedback polynomial: x^16 + x^14 + x^13 + x^11 + 1 bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5) ) & 1; lfsr = (lfsr >> 1) | (bit << 15); for (mask = 0xF0; mask; mask >>= 1) putchar('0' + !!(lfsr & mask)); return lfsr; }
  21. Generate serial data

    Hi, I just bought the Analog Discovery 2 and I was looking for a way to generate serial data(uart, spi) to test my projects through the digital output pins. I was wandering since there is a logic analyser and interpreters for serial communication data. Thanks for you help
  22. Maximum rate of ARTY USB-UART

    Hi, Does anyone know ARTY's maximum data rate using the USB-UART? Thanks.
  23. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  24. Arty: Display UART data on LEDs

    Hi all I have a very simply UART TX/RX pair I have built in Verilog, and have been struggling to get them to function on the Arty Board. I can connect the two together to form a simple "echo" function, where any received RX data is immediately sent out on the TX module, but beyond that I can't correctly see the values I send to the Arty. I tried simply piping the received byte to the LEDs on the Arty board, but the values lit up do not correspond at all to the ones I expect. Sending the character string "AaA" does not make the ascii encodings for "A" and "a" appear on the LEDs. However, I do get the right characters echoed back to my PuTTY terminal. My code for the project can be found here: https://github.com/ben-marshall/uart You'll need: rtl/uart_rx.v , rtl/uart_tx.v, rtl/impl_top.v and constraints/default.xdc to re-create the project. I'm using Vivado 2016.4 on Ubuntu 16.04. Thanks, Ben
  25. Hello Digilent Community! I just finished putting the finishing touches on a UART demonstration project that you can find here. The project was originally intended to share a C++ class that could work with Verilator to prove that anyone's UART implementation was working. However, after I got into it, I realized the project had a lot of value that others might appreciate. As an example, consider this post by @martin16. Had he used any of the testing mechanisms listed below, he might have known which side of the RS232 port he was working with was at fault. The core contains a complete implementation of both a transmit and receive UART encoder/decoder. These can be easily taken from my project and placed within your own. (Subject, of course, to the limits of the GPL v3) The core also contains a (fairly) generic FIFO implementation. For those wondering how to implement a FIFO, you may find this valuable as well. For those who would rather interact with a serial port over a bus, such as the wishbone bus, there are two approaches within the project that can be used to hook it up to a wishbone bus. One can be used within a larger wishbone slave module, the second as a standalone module. Both are Wishbone B4 compliant, and both use the pipeline mode--allowing you to read/write multiple values on consecutive clocks from/to the controller. Of course, this only really makes sense when using the FIFO. Those might be valuable enough on their own, but you can probably find without too much additional work other implementations of the above. Therefore this project includes some even more valuable files: It includes a series of test programs/configurations that can be used to determine if the hardware on your board is working properly. If you are like me, you've struggled every time you've tried to get a serial port working on a new board. Should you connect your output to the TX or to the RX line? Do you have the UART set up properly, at the right baud rate? Can you handle more than just single values at once? How fast can you transmit/receive? To help you answer these questions, the project file contains the following test configurations: Hello World: You know, that old fashioned hello world program? I would recommend trying this program on your board after you can blink an LED at your favorite rate, or equivalently after you know that your clock works. This particular project is so simple that it depends upon only the clock input and the UART transmit output. Getting this program running on your board will demonstrate that you understand your clock, and that you can modify your I/O constraint file properly, and that you know how to connect a terminal program to your board in order to observe the results. Line Test: Once you've got a hello world program running, so that you know the output UART pin works, then it is time to test the input UART pin. This is the purpose of the line test testing program. It works by reading a line of data (either until a newline or 80--characters), and then dumping that line to the output. (Don't forget to turn off hardware flow control, and be aware of the differences between a new line and a carriage return!) SpeechFifo: Finally, there's a program that can be used to test the FIFO capabilities found within the wishbone UART peripheral. This program uses the FIFO capability to make certain the transmitter stays fully loaded for over a thousand characters of output bytes. (No, this isn't computer speech generation, but rather a computer dumping a Abraham Lincoln's Gettysburg Address across the UART port.) Each of these configurations has a corresponding Verilator simulation file associated with it, allowing you to simulate the functionality within them as part of Verilator. The project includes, like I mentioned above, a C++ class that can be used to determine if your own UART is transmitting correctly under a Verilator simuation. This class can also be used generate UART signaling in order to test if your RTL can receive it properly. (See the line test C++ harness discussed below for an example of this.) As complements to each of the testing configurations above, the project contains C++ files to drive each of those within a Verilator context. Some unique features include: The Line Test C++ test harness automatically generates a linetest.vcd file that can be used together with GTKwave to study how the core works. Further, it can be run in either an interactive or an automated mode. The Speech Test C++ test harness can be used in an automated mode, or with the -i switch in a more interactive mode. In this latter mode, the speech test program generates a speechtrace.vcd file that can be used with GTK wave to understand how the UART transmitter, FIFO, the wishbone bus decoder, or even the test harness itself. I hope you find these as valuable as I have. Please feel free to post any questions or comments you might have about this project below. Dan