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Found 57 results

  1. Vonmuller

    Custom Function Generator

    This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  2. K_Ashish

    UART Interrupt in zybo queries

    Hello, I am trying to use UART in interrupt mode using zybo board. I tried Hello World example using UART1 of PS which is 48 49 MIO and it is working. I referred interrupt example in ~\Xilinx\SDK\2016.2\data\embeddedsw\XilinxProcessorIPLib\drivers\uartps_v3_1\examples. But I am not connect uart with Interrupt controller or GIC. Any suggestion on designing hardware in vivado and which reference code to use?
  3. bri

    nexys 4 ddr UART

    What is max baud rate of UART on Nexsys4 DDR board? Datasheet for FT2232H indicates slower speeds when using RS232. I looked on schematics for Nexsys4 DDR and don't see part so couldn't check how it is actually wired up. Also trying to understand end-end application to FPGA connections in terms of flow control. Trying to bring data into board through RS485 PMOD that I can't flow control so thought I might be able to use FPGA to manage flow control and output data out of UART to host PC and store to file. Trying to understand max data rates, how much buffering I need in FPGA, etc. Not sure if processor running software on FPGA would be better or just implement in hardware.
  4. Dear all, I'm trying to integrate Pmod GPS on my Xilinx ZCU102 platform with a Linux OS. To do so, I'm using the resources available in Digilentinc's vivado-library zip (PmodGPS_v1_1 IP + software drivers using xuartns550). I managed to make it work correctly in polling mode (calling GPS_getData func) with a clock freq of 49.995 MHz and a baudrate of 9600 symbols/s. Nonetheless, when I try to increase the baudrate to 115200, the NMEA messages in the ->recv buffer get corrupted. For instance, some messages are not correctly formatted because one comma has been flipped to another char and it makes the GPS_formatSentence function to seg fault. It's really important for my project to achieve higher rates (I'm working on a 60 fps camera and I would like to associate a GPS data to each frame and can not afford to spend too much time in the GPS_getData function in I want to preserve real time operation). Here are the hypothesis I make on the cause of this problem: a) The clock at both ends of the UART link are not synchronized. As far as I understand, this problem can also occur at low baud rates so it's probably not the main cause (cf PercentError computed in XUartNs550_SetBaudRate). b ) There is corruption on the physical link (my PMOD in connected to the ZCU102 using female-female jumper wires). Here are the workaround I tried so far: a) Check the checksum of the NMEA message before calling GPS_formatSentence and discard corrupted messages. This improve the reliability of the system but some problems still appear from time to time which is definitely not acceptable. I feel like it will be quite complex to design a check that is able to handle any kind of corruption (what if a $ sign or a * gets corrupted ?) b ) Use baud rate = 9600 and call GPS_getData and GPS_formatSentence in another thread (so that the main thread is not waiting for GPS_getData to complete). Unfortunately, I only have little experience in multi-threaded programming and I did not manage to make it work properly. I also think it's not very good practice, it would be better to make it work at higher baud rates. Do you have any complementary idea about how to fix that ? Thanks in advance, Alexandre
  5. Hello, So I am trying to write a script that will be taking advantage of both output and both inputs to the AD2 as well as take select information and send it out to two (for now) serial lines. I have written a script to control everything I need minus the actual setup of the UART settings, sending the data over the Tx line and receiving over the Rx line. Are there any examples of how to send the data over script as opposed to using the built-in GUI of Waveforms? Thanks, Ryne
  6. Brooklynoutlier

    Problem with UART, Arty S750 to Windows 7 SP 1

    Anyone else experienced a problem with communicating to an HP laptop running Windows 7 SP 1 from an Arty S7 50 through the UART port? I boiled the application down to just two simple modules, but I still get an extra character (x"FF") added to every character sent from the board to the laptop. In other words, trying to send "01234" from the board results in "0ÿ1ÿ2ÿ3ÿ4ÿ" being received (ÿ has ascii value xFF). I've tried reinstalling drivers using files from the FTDI site, and tested with two different terminal programs (PuTTY and Termite), but the result is always the same. Communication in the other direction works just fine.
  7. Hello I am a user of Analog Discovery2 and I believe it is missing one very important (for me at leas) function. I basically want to monitor and register the communication between two devices which use UART to do so. The Protocol panel looks great but I am able to register only one of the devices at the same time. Logic panel is very unfeasible in my case because I want to register many lines of the communication (like 5 min). Is there any way I can achieve that? Maybe there is a custom script which would help in my case?
  8. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  9. Hi, I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP. The AXI Uartlite is configured as follows. CLK 1MHz, baud rate 9600, data bits 8 S_AXI_wvalid <= '1'; S_AXI_wstrb <= '1'; S_AXI_awvalid <= '1'; S_AXI_aresetn <= '1'; S_AXI_awaddr <= "0100"; S_AXI_wdata <= "00000000000000000000000001010011"; When I simulate, the TX port output of AXI Uartlite just remains ‘X’ state instead toggling as per S_AXI_wdata. I have simulated upto 4 seconds and ll the values are initialized from the beginning of simulation. Am I missing any configuration setting? or anything needs to be carried out to get teh data at TX port ? Help is much appreciated. Regards, Subash
  10. Weevil

    32bit data transfer using uartlite

    Hi all, actual i try to transfer a data stream from the DMA via uart to my PC. In my design an DDS-compiler generates a 32bit sine wave, which should be transfered via uart and read by a python script. The general data transfer works, but sometimes i get some noisy signal. This signal happens also when using a lower sample rate. For the uart data transfer actual i did not add any marker where the 32 bit value begins or ends. So i expect this is the problem, but i don't know how to include this in my SDK and python code. Maybe any suggestion? (The FPGA design is similar to my previous post https://forum.digilentinc.com/topic/8966-axi-dma-timing/?page=0#comment-26920 using the Cmod A7) Plot of the result with pyqtgraph: SDK code: int XAxiDma_Poll_Uart(u16 DeviceId) { int Status, Index; int Tries = NUMBER_OF_TRANSFERS; u32 *RxBufferPtr; u32 *RxPacket; u8 BytesSent; RxBufferPtr = (u32 *) RX_BUFFER_BASE; RxPacket = (u32 *) RX_BUFFER_BASE; for (Index = 0; Index < MAX_PKT_LEN_WORDS; Index ++) { RxBufferPtr[Index] = 0xCC; } /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache is enabled*/ Xil_DCacheFlushRange((u32)RxBufferPtr, MAX_PKT_LEN); Status = XAxiDma_SimpleTransfer(&AxiDma, (u32) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); if (Status != XST_SUCCESS) {return XST_FAILURE;} while (XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)) {/* Wait*/} /* Invalidate the TestBuffer before receiving the data, in case the Data Cache is enabled*/ Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN); //send data to uart BytesSent = XUartLite_Send(&UartLite, RX_BUFFER_BASE, sizeof(RxPacket)); while (XUartLite_IsSending(&UartLite)) {/*Wait*/} return XST_SUCCESS; } Python code: import numpy as np import sys import serial buffersize = 512 byte_number = 4 ser = serial.Serial( port='COM6',\ baudrate=921600,\ parity=serial.PARITY_NONE,\ stopbits=serial.STOPBITS_ONE,\ bytesize=serial.EIGHTBITS,\ timeout=0) for u in range(20): #read serial buffer s = ser.read(buffersize) #convert to integer for i in range (int(len(s)/byte_number)): res_value = dataSerial[(i*byte_number):((i+1)*byte_number)] value = int.from_bytes(res_value, byteorder='little', signed = True) dataSerialFormated = np.append(dataSerialFormated, value)
  11. Hi folks! I'm thinking of buying an Analog Discovery 2. One piece of functionality I need is sniffing a serial connection between two devices. Not just a set number of samples - I mean capturing both TX and RX bytes to file/PC memory, for however many hours I need to catch my nasty little bug. The actual amount of data transfered is low. I'm actually utilizing maybe 30% of the capacity, at around 10kB/s TX and RX. On top of that, I'd like to add support for my custom software protocol that's running on the UART. Kind of like in wireshark you can see what a packet is, not just a plaintext context-less byte barf. If waveforms doesn't support this, I'm completely fine with writing an utility that, say, takes raw UART data over loopback TCP and formats it externally. Is this possible on the Analog DIscovery? What settings should I be using to make it work like that?
  12. John_Anacall

    Questions about how to use UART

    Once again I'm sorry if I'm asking what can be considered silly questions, but I'm diving into the FPGA world by myself and I'm having serious dificulties finding documentation or examples that fit my questions. I'm using a Cmod A7 and I want to develop a GUI to let the user define some parameters. Through what I've been researching I believe the way to do it is using UART with the micro usb of the board. I've seen some examples of UART implementations, some I found in responses here on the forum, but due to my lack of knowledge it seems to me they lack important things so I could understand them. So I'll ask two questions: 1 - I believe that if I want to let the user change some parameter, that parameter must be a register and I need to know its adress. But how do I define the adress of that register? I haven't been able to find any example for this. 2 - It seems that the Cmod A7 has two UART ports according to the XDC file, so exactly how am I supposed to use them? Will that make a diference from examples like this one? João
  13. theUltimateSource

    cannot connecto to terminal on Zybo Z7

    Hello, just plugged in my new Zybo Z7 471-015 but cannot connect to serial port. It works on the Zybo. PROG UART is connected to USB PC BSP stdin, stdout is set to ps7_uart_1 I have no other application open that is accessing the serial ports to make sure I dis- and reconnected the Zybo Z7, still doesn't appear on the port list Zybo Z7 appears as USB Serial Converter A and B in the device mngr restarted PC tried another USB port replaced USB cable, both are data cables JP6 is set to USB JP5 is set to JTAG drivers had been installed with Vivado 2017.2 re-installed Vivado 2017.2 cable drivers, restarted PC USB port should be listed even without any PL configuration loaded, right?
  14. Weevil

    Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dds-compiler over the Stream-Data-FIFO to the FFT right?
  15. Hi, I want to understand the main difference when programming a board which is configured using a BSP (Ex: ZYBO) and which is configured using only device details(Ex: xc7z010clg400-1). I'm asking because I'm configuring only zynq in the block design with uart1 for hello world application. If I program using ZYBO bsp it works but not if I use only the device details. I need to understand this since my actual project is on a custom z7010 board and not a regular development board and I'm not able to get the uart up and running. I wanted to figure it out on a development board as it is easier to understand. I think it is some simple settings detail that I'm missing. Appreciate any help.
  16. cristian_zanetti

    uart receiving module for 16 or more bits

    Good morning everyone, I am currently developing a computer application in Matlab with help of VHDL and the Nexys 4 DDR, my problem is that I need to send a vector of 16 or more bits through an aurt module, the aurt module only sends 8 bits but I need to send more bits. anyone have any idea how to receive more than 8 bits per aurt? , I know that you should make the matrix reception module in vhdl and I was trying with this module that I have, but it does not work, and I have no idea how to do it to receive matrix. thanks. recepción.txt
  17. Hi, While there are many examples showing a basic Hello World using a Zynq UART, how do we read in data from the console using the same UART? Can anyone please guide me to the right example. I cudn't find one.
  18. fpgauser

    motor controller with BASYS3 and UART

    Hi everyone, I am working on a project about drone. The project is sending and receiving data through UART and controlling the four brushless servo motors by getting these value for the speed of servo motors. I could find and combine codes for accomplishing the communication between fpga and the computer. However, I cannot make a relationship between coming data with servo motor. I get the coming UART data one by one by converting integer for duty cycle. Could you help me out this, how can I get the received data and send it to servo motors? Thanks in advance.
  19. cristian_zanetti

    UART and XADC

    Good morning, I am currently developing a graphical interface that allows visualizing the XADC data of the NEXYS 4 DDR, I found the problem that the UART communication protocol sends 8 bits as information, the xadc samples to 12 bits, someone knows some idea, solution or module that allows me to send the 12 bits of xadc by uart? Thank you
  20. Hello. I have to adjust the speed (baud), parity bit (if I want), stop bit. For both software alike. I would like to know if anyone has that code in VHDL / VERILOG ? (UART/JTAG)
  21. cristian_zanetti

    UART communication protocol in nexys 4 DDR for XADC

    Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  22. HansV

    Protocol

    Hi, In the Protocol tool, the UART tab The ´Receive to File´ and ´Save´ button generate a windows error by me. Thanks in advance, Hans
  23. jacobfeder

    Arty Z7-20 hello world / BSP regeneration

    I'm trying to get the Arty Z7-20 board to simply print "hello world" to the SDK terminal. I have the board files installed from GitHub. I made a vivado project with the Zynq PS and a few random IPs. The PS is configured to use UART0 (mio pins 14/15). When I run the hello world example in the SDK, I don't get anything on the COM port and the TX/RX LEDs don't light up. There are 2 COM ports that SDK detects (3 and 4). If I try to connect to 3 it says it's already connected. I'm assuming this is the because it uses COM3 for downloading the program. So I connect to COM4 @ 115200. Any ideas on how to debug this issue? Thanks EDIT: I was able to get it working---the issue was resolved by deleting and regenerating the BSP in SDK. I've never had to do this before as SDK has done all of the regenerating automatically. Can someone explain a bit why/when it is necessary to regenerate the BSP?
  24. Hello, I would like to know if the PL in Zybo boards can be used for a HDL FPGA design without the Zynq PS (no software). Is there some reference/demo/example about this case? Particularly, I want to know how to connect the USB-UART port to a custom HDL (UART) Module in the PL section, but using the same pins (i.e. MIO48, MIO49) that Zynq normally uses. Thanks in advance
  25. Zoltán Lehóczky

    Nexys 4 DDR shows up with two COM ports

    We use Nexys 4 DDR boards for testing our platform. While with most of the Windows host PCs there are no issues, with one of our clients' when the board is plugged in (using the supplied micro USB cable) it shows up as two COM ports under Windows's Device Manager. We suspect this is behind that we can't properly run Xilinx SDK programs on the board, the debugger looses the connection. Is it normal that the board shows up as two COM ports? (When the board is de-attached the ports disappear, so both are surely the single board.) If yes, can this cause issues? If now, how can we begin to troubleshoot the problem, what can possible be behind it? Thank you in advance!