Search the Community

Showing results for tags 'tutorial'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 23 results

  1. Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky. Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation" The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete. The log gives the following in "Message:" (attached) Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in ca
  2. Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-programming-guide/start). I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the s
  3. I am going through the Zynq Book Tutorial, version 1.3 April 2014. It seems the Zynqbook and Zynqbook Tutorial are leveled at Vivado 2014.x Zedboard and I have Vivado 2017.2 and Zybo Z4-20 board. Following example 1.B for the Zedboard, the tutorial states on page 15, "Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO." Then a dialog box labeled "Run Connection Automation" will appear. In my version of VIvado or Zybo constraints I don't get this popup window or a selection the looks like /axi_gpio_0/GPIO a
  4. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its
  5. Here my experience with the Cmod A7-35T evaluation board and the MMCM module, take a look and report me if I've to chage somethings, hope it can help. Due to the size of the document (3.5 Mb due to lot of screenshoot) I've to put this one for downloading from my dropbox, for this reason I kindly ask to some admin to let me know if I can or not put inside a download link to my dropbox folder in order to share the tutorial. Thank Best regards
  6. Hi I have a general question about how to try out tutorials, demos, and just how to look at a project folder. When I open a tutorial/demo/project that I download from github, I always see a bunch of folders with the same names: hw_handoff, proj, repo, sdk, src, among other things. Can someone please explain these names, and maybe names of other folders that I may see in other projects? Are the contents of these folders dependent on each other? Can I implement the project with just one? How do I use these folders? Thanks
  7. Colin

    Zybo tutorial help

    i currently have a project where i need to produce a tone from a zybo board and to familiarise myself with the board i downloaded the pdf from http://www.zynqbook.com/download-tuts.html and the zip files but and i do the tutorials step for step but when i try to run the programme on the board nothing happens im using vivado 2017.1 i have the ports set to 115200 baud when i import the c code i get a warning from xparamaters.h i asked my project manager and they said its because im not using costraints but the turtorial specifically mentions not using constraints can anyone tell me w
  8. Zygot goes back to the future to transfer data between two FPGA boards at 600 MB/s. Along the way he has a debugging adventure, learns ( AGAIN!!! ) why free stuff rarely is free and remembers when Digilent made FPGA boards that were great for development projects. This is a nice project for beginners or old hands to read through even if you don't have the hardware. CAUTION!!! You must read through the README text file before trying to replicate this project in hardware. Release 2 fixes some bad commentary in the source files and improves the behaviour of the UART transmit
  9. So, I just received my Digital Discovery earlier this week. I've actually got a project coming up where I'll be able to make use of it, so thought I'd familiarize myself with the differences between it and the Analog Discovery. I proceeded to walk through the protocol tutorial that uses the ALS PMOD to demonstrate SPI interaction. I had never tried this with the AD2, and figured it would be a good test. Unfortunately, after checking my work multiple times, I was still only getting back 0 signals. Thinking the problem could be the DD, I tried the same thing on the AD2 with the same results
  10. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear.
  11. Good afternoon I am learning to use VHDL. I have a Nexys 4 ddr and a PmodSD card, that I would like to learn to use. I downloaded the most recent version of VIVADO, and Xilinx as well. Do you all have a program that I can use, to see how it works or a tutorial to process images? I would appreciate it. Thank you. Kind regards.
  12. Hi all, I am currently doing the Xilinx tutorial to run Linux on my zybo : http://www.wiki.xilinx.com/Build+FSBL In the process, I have to get these task done : Bitstream (for the programmable logic portion) System hardware project hdf file My question is : can I use the https://reference.digilentinc.com/_media/zybo/zybo_base_system.zip ...to generate the bitstream and the system hardware project ? If I complete the tutorial with the generated files, will I be able to run linux and use it with the hdmi or vga output, get access to any kind of command prompt?
  13. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  14. Hello guys, this question is aimed primarily at Digilent staff but if anyone has an answer, I'm not choosy :-) I just got a CMOD A7 and I'm bringing it up by going through simple projects and tutorials. I'm stumped by this one : https://reference.digilentinc.com/learn/programmable-logic/tutorials/cmod-a7-getting-started-with-microblaze/start I've followed it to the letter, but reality diverges from the internet at step 13. There is nothing in my SDK's "Run As" menu. Why is that, and how can I fix this ? The whole tutorial never mentions the reset signal : how is it generate
  15. Hi everyone, I know that the CPLD starter board that features the XC2C256 is deprecated but can someone provide a few links with a "hello world" application? A blink LED or anything to get me started and at least check if I have my toolchain set up properly. Also, I am using xilinx ISE webpack but a few people have mentioned that vivaldo might be a better choice because xilinx doesn't support coolrunner anymore through webpack(?). I see the devices on the device list so I don't understand why I should use vivaldo. Thanks!
  16. Hi, I have a friend who has bought a Basys 3 and has done some great projects in HDL, but he wants to step it up a notch and try something with MicroBlaze. Although I'm willing to help him I don't have the time for it so I thought about sending him some tutorials on MicroBlaze and GPIO using block design and Vivado. The only problem is that there are no coherent tutorials for this and the ones I found to be decent where for EDK. To be clear I'm not looking for a board specific project, all I want is on tutorial which shows a beginner how to use a GPIO with MicroBlaze in Vivado.
  17. Hello, I just recently bought a zybo board and was following the digilent tutorial and almost finished the getting started project. However, I cannot make the helloworld.c file after launching the SDK. I can still program the PL side, but if I cannot utilize the PS side. SO now I basically have a standard FPGA until I can get this issue resolved. I have been looking through the xilinx forums too and haven't seen a good solution to this problem. here is an example of the console output and a screenshot of the error message that pops up Building file: ../src/helloworld.c Invoking: ARM gcc compi
  18. Dear Community. I've recently bought a Zybo Zynq board and i'm having some getting started problems. Im known with both C and VHDL programming before but i've never had such a multi-purpose FGPA, dualcore board before. I tried following some basic tutorials, like: https://reference.digilentinc.com/zybo:gsg http://www.zynqbook.com/ and several youtube led blinks. But I'm experiencing different problems with all of them. My board isnt listed in the Vivado 2015 > new project > boards list I can't find the right settings to get the leds to the GPIO Or when I find a "pre made tutorial led bl
  19. Hi there, I recently purchased a Zybo Zynq 7000 development board and have been working through tutorials to familiarize myself with Vivado, IP blocks, etc (not a ton of experience with FPGAs). I have used the base system design included and successfully was able to display images from the HDMI out on the board using an included demo. For the project I have in mind, however, I really want the HDMI port to function as a receive/sink port rather than transmit/source. All the other peripherals configured in the base system design are perfect for my application aside from the HDMI. Is there a w
  20. gmv

    Nexys4 ddr resource

    Hi, are there some news about nexys4 ddr resource time to release of Embedded Linux Materials and Advanced Microblaze Design with MIG, Ethernet, UART & GPIO ?
  21. I am following the instructions in the Embedded Linux Hands-on Tutorial and got stuck at step #3 in section 4.2. The step #2 is successful with the following output : make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o SHIPPED scripts/kconfig/zconf.tab.c SHIPPED scripts/kconfig/zconf.lex.c SHIPPED scripts/kconfig/zconf.hash.c HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf # # configuration written to .config # The command in step #3 gives the following error : make ARCH=arm CROS
  22. Hi guys, I have been writing PC software for the last 15 years and I now wanted to take a shot at FPGA, I have bought myself the basys3 board and installed the viva do software, I followed the instructions for the Digilent abacus demo, this is a simple binary calculater to show some very basic functions, I Immediately noticed this takes aboud 15minutes before the program can be transferred to the basys3, I understand that synthesis takes some time but 15 minutes seems to much for what my patience can handle, taking into account that the abacus is a simple and uncomplex program, what wil
  23. Does anyone know how I can get the images used in the Bootloader Tutorial (see image below)? The file is located here: http://www.digilentinc.com/Data/Documents/Product%20Documentation/chipKIT_Bootloader_Tutorial.pdf Thanks