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Hello ! We are designing a high-speed bus on a PCB interfacing the Arduino/Chipkit GPIO pins onboard the PYNQ-Z1. Inorder to maximize the signal integrity parameters, we would like to optimize the trace lengths in our board based on the trace information and the layer stackup details of the PYNQ board. It would be really kind if someone from Digilent could share this valuable information to assist our optimization. Regards, r4d