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Found 7 results

  1. I believe the clock latency is the total time it takes from the clock source to an end point. PFA Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture? Thanks Tip
  2. I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z] Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png Thanks
  3. Hello, I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning: [Timing 38-282] The design failed to meet the timing requirements. According to the Timing Report this warning refers to the Path from "hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C" to "hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D" with source clock mmcm_clkout1 and destination clock dvi2rgb_0_PixelClk. The reported slack is -0.787. Any timing constraints of this should have been provided by Vivado automatically, so what could I do about this warning? I tried this on three different machines, always getting the same critical warning. Eff
  4. Hello again! I'm trying to use the AD2 to act as both a signal source (wavegen1) and a measurement (scope1) device for the purpose of tracking conduction delay of the signal. Currently, I simply have the wavegen1 connected directly to scope1 with 3 cycles of a sine wave being put out. I am aware of the measure command to find the maximum on my scope1 but I was wondering if there was a way to find N (3 in my case) maximums AND find the corresponding times with respect to the timing of wavegen1? I plan to assume the timing of the wavegen1 is relatively accurate to my input frequency and can find the theoretical maximum thus having the initial time from which to subtract from my scope1 maximum times. Code thus far function doPing(){ print("Amplitude and Time Delay Recorded"); // User Inputs var Freq = 5e3; var Amp = 1.0; var N = 3; // WaveGen Settinngs Wavegen1.Synchronization.text = "Synchronized"; Wavegen1.States.Trigger.text = "None"; Wavegen1.States.Wait.value = 0; Wavegen1.States.Run.value = N/Freq; Wavegen1.States.Repeat.value = 1; Wavegen1.Channel1.Mode.text = "Simple"; Wavegen1.Channel1.Simple.Offset.value = 0.0; Wavegen1.Channel1.Simple.Amplitude.value = Amp; Wavegen1.Channel1.Simple.Frequency.value = Freq; // Scope Settings Scope1.Trigger.Trigger.text = "Repeated"; Scope1.Trigger.Type.text = "Auto"; Scope1.Trigger.Source.text = "Wavegen 1"; Scope1.Trigger.Condition.Text = "Rising"; Scope1.Trigger.Level.value = Amp/2; // Start instruments Scope1.run(); wait(0.1); Wavegen1.run(); // Measure var maximum = Scope1.Channel1.measure("Maximum"); print(N+" Max: "+maximum+" V"); //Want to do for 1:N and get time and amplitude with relation to time zero being the zero of the wavegen //Close out instruments Scope1.stop(); Wavegen1.stop(); } if(!('Wavegen1' in this) || !('Scope1' in this)) { throw("Please open a Scope and a Wavegen instrument"); } doPing();
  5. Hi fellow labview users, i need expert developing a system, what my system do is like power timing system, set timing for what time the light to turn on and off, the problem is that while i know how to get real time and date from pc itself, i dont know how to link the timing setting to real time, maybe the printscreen can explain better? I would appreciate for a swift reply, thank you.
  6. Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segments will still not be visible - I just want to demonstrate the timing problem. However, the design fails to meet timing constraints as follows in attached pictures: Timing constraint failures in more detail, including the full source VHDL: Clock routing on the FPGA: The following is the .xdc constraints file (commented-out definitions are omitted): From what little I know about FPGA clock routing and resources, I understand this to be due to the high-frequency clock and associated logic being in different regions to each other, thus requiring the implementation run to route the clock signal through awkward paths; as a consequence, the total signal propagation time is such, that before the logic relevant to the current clock pulse is evaluated, the next clock front is already present. Am I correct in this thinking? And in either case, how can I fix the timing issues that Vivado warns about?
  7. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture of the the system I obtained at the end but this website would not let me. Any way, my system matches exactly the one in the tutorial. The validation passed, synthesis also passed ( although it gave me the same error the tutorial asked me to ignore, which I did). However, before running implementation I ran a "Report Timing Summary" from the Synthesized Design sub-menu, It gave me the several errors related to the oserdes_clk... To make sure these errors were not caused by something I may have entered wrong while creating the project, I decided to re-do the project starting from a blank slate, but the results were exactly the same in the new project. I tried to paste here an image with the errors but this website would not let me .... Anyway, the errors were Inter-clock paths / oserdes_clk to oserdes_clk / Hold -0.246ns (10 occurrences) Below is one of the Interclock paths that had the Hold timing error From: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK To: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST I think the error is due to a lack of one or more timing constraints. I suspect there might be an error with the board files associated to the Nexys-Video board, specifically related to the MIG7 and the DDR . I do not have enough knowledge of the system to be able to make the constraints myself. How could I solve these timing errors? Thanks