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Found 11 results

  1. Hi all, I am seeing an issue on multiple Digital Discovery devices, where the timing precision is off by over a percent (where I'd expect 10—100ppm, at least 2 orders of magnitude better). The problem can be seen most easily by having the device generate a simple 50% duty cycle clock on one of its output pins, e.g. 1 kHz. On two different Digital Discovery devices I tested, the scope reports a frequency of below 990 Hz. The signals otherwise look as expected (good level, stable, good edges) apart from the bad frequency behavior. I confirmed the measurement with a high-quality Keysight 53230A frequency counter. Also, repeating the same measurement using an Analog Discover 2 shows the expected performance (1 kHz accurate to about 10 ppm, which is pretty good for a non oven-controlled crystal oscillator). I have attached screenshots of what I'm seeing for one of the Digital Discovery devices below. The other one is similar (showing about 987 Hz instead of 984.5 Hz). You can already see on the scope that the signal isn't a nice 1 kHz, and the Keysight measurement confirms that quite unambiguously. It should also be noted that the Keysight measurement shows that the signal not only has an unexpected frequency, but also that it isn't as stable as one would expect. I can provide serial numbers of the devices I tested and perform measurements if this helps to pinpoint what's going on here. Any help would be appreciated. Given my very positive experiences with the AD2, I can't believe that what I'm seeing is within spec. On the other hand, I verified this with two different DD devices purchased over 6 months apart, so it looks like I'm not just looking at a single faulty device. As a side node, it seems I'm seeing the same thing on the inputs; if I sample a high-quality externally generated 1 kHz clock (coming from an SRS FS740), the timing seems noticeably off. However, Waveforms doesn't provide an easy way to display the trigger rate counts as far as I am aware, so I want to focus on the clock generation problem first, because that's much easier to verify and reproduce. If anyone else can repeat this simple measurement and share their findings that would be great! Best regards, Sidney
  2. I am working with an Arty design and I have noticed that while I have no intra-clock timing failures, I still have high severity warnings in the "check timing" portion of my timing summary related to not having constraints for input and output delay (no_input_delay and no_output_delay). Does digilent provide suggested timings for the on-board peripherals (like Ethernet and flash), or do I have to go through all the datasheets myself and estimate the trace delay? I found this thread from 2017, but the question was never resolved.
  3. Hello, my name is Caleb. I am a senior electrical engineering student at Northern Illinois University. I am using the Analog Discovery 2 in order to capture analog pixels sent from a sensor at 5MHz and then interpreting that data on the Raspberry Pi 4. I am running into questions with the timing of the logging function of the oscilloscope on the Analog Discovery. I have noticed that when I send multiple acquisitions at once I run into issues with the timing on the next acquisition. It seems that each acquisition comes in order, but there is a delay between the end of one and the beginning of the next. For example, the time from the first sample to the last would be about 1.6 ms elapsed time. However the next acquisition would have a DateTime listed that is 50 ms later than the previous aquisition. My current settings I have been using are: Scope mode - Repeated Buffer: 10 (Not sure from the source material how this impacts acquisitions..) Logging Execute: Each acquisition 8192 samples Is there a way to have the acquisitions send the data out so that the end of acq0000 would correspond to the data at the beginning of acq0001? An additional question I have is how the AD2 Date Time function is working in the csv files exported as acquisitions. Is it a real time clock on the AD2 or is it information pulled from the pc/rpi? Thank you for any help you are able to provide on this. I can provide further information if it is needed.
  4. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem. So the data transmission is initiated by NODE A and the control is with NODE A. NODE A will Enable the data transmission for all four UARTs. Now the problem which i am facing is, when NODE A enables the transmission for any two of the UART lines the data transmission is smooth, the problem arises only when i enable the other two. Which means the zybo is not capable of attending to those interrupts which is simultaneously coming from NODE A through four UART lines. My data contains Start byte and Stop byte, Both Start and stop byte are same character. I will attach a my Interrupt handler for reference. **************NOTE************** UART IP on PL side : UART16550 Type of UART : Interrupt driven. Software used : Vivado 2018.3 and SDK Bare metal software. UART interrupt priority : equal priority for all four UARTs. ********************************** I am not very sure about how to use four UARTs efficiently with my Zybo . Please help me with the problem, any inputs from your side will be appreciated. The following is my UART interrupt handler. *************************************************************************** static void RW1RecvHandler(void *CallBackRef, unsigned int EventData) { int i, ch, RecvCount, index; RecvCount = EventData; // repeat this loop for all chars received, i.e., for all ReceivedCount i = 0; while (i < RecvCount) { ch = RW1_RecieveBuffer[i++]; // get the received char from the buffer if(RW1_Start_byte_flag == 1) { // Stop Byte Check for RW1 if (ch == 0xc0) { // Ignore one of the two successive start byte characters if (RW1_ReceivedCount > 1) { RW1_Start_byte_flag = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; RW1_Frame_complete_flag = 1; } } else { if ((index = RW1_ReceivedCount) < TEST_BUFFER_SIZE) { RW1_Buffer[index] = ch; RW1_ReceivedCount++; } else RW1_Start_byte_flag = 0; } } // Start Byte Check for RW1 else if (ch == 0xc0) { RW1_Start_byte_flag = 1; RW1_ReceivedCount = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; // Note the cpu time when first character is received XTime_GetTime(&t_start_RW1); RW1_Frame_complete_flag = 0; } } if(RW1_Frame_complete_flag == 0) { // set up the buffer for next char in interrupt mode XUartNs550_Recv(&RW1, RW1_RecieveBuffer, 1); } } Thanks & Regards Ajeeth Kumar
  5. I believe the clock latency is the total time it takes from the clock source to an end point. PFA Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture? Thanks Tip
  6. I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z] Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png Thanks
  7. Hello, I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning: [Timing 38-282] The design failed to meet the timing requirements. According to the Timing Report this warning refers to the Path from "hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C" to "hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D" with source clock mmcm_clkout1 and destination clock dvi2rgb_0_PixelClk. The reported slack is -0.787. Any timing constraints of this should have been provided by Vivado automatically, so what could I do about this warning? I tried this on three different machines, always getting the same critical warning. Eff
  8. Hello again! I'm trying to use the AD2 to act as both a signal source (wavegen1) and a measurement (scope1) device for the purpose of tracking conduction delay of the signal. Currently, I simply have the wavegen1 connected directly to scope1 with 3 cycles of a sine wave being put out. I am aware of the measure command to find the maximum on my scope1 but I was wondering if there was a way to find N (3 in my case) maximums AND find the corresponding times with respect to the timing of wavegen1? I plan to assume the timing of the wavegen1 is relatively accurate to my input frequency and can find the theoretical maximum thus having the initial time from which to subtract from my scope1 maximum times. Code thus far function doPing(){ print("Amplitude and Time Delay Recorded"); // User Inputs var Freq = 5e3; var Amp = 1.0; var N = 3; // WaveGen Settinngs Wavegen1.Synchronization.text = "Synchronized"; Wavegen1.States.Trigger.text = "None"; Wavegen1.States.Wait.value = 0; Wavegen1.States.Run.value = N/Freq; Wavegen1.States.Repeat.value = 1; Wavegen1.Channel1.Mode.text = "Simple"; Wavegen1.Channel1.Simple.Offset.value = 0.0; Wavegen1.Channel1.Simple.Amplitude.value = Amp; Wavegen1.Channel1.Simple.Frequency.value = Freq; // Scope Settings Scope1.Trigger.Trigger.text = "Repeated"; Scope1.Trigger.Type.text = "Auto"; Scope1.Trigger.Source.text = "Wavegen 1"; Scope1.Trigger.Condition.Text = "Rising"; Scope1.Trigger.Level.value = Amp/2; // Start instruments Scope1.run(); wait(0.1); Wavegen1.run(); // Measure var maximum = Scope1.Channel1.measure("Maximum"); print(N+" Max: "+maximum+" V"); //Want to do for 1:N and get time and amplitude with relation to time zero being the zero of the wavegen //Close out instruments Scope1.stop(); Wavegen1.stop(); } if(!('Wavegen1' in this) || !('Scope1' in this)) { throw("Please open a Scope and a Wavegen instrument"); } doPing();
  9. Hi fellow labview users, i need expert developing a system, what my system do is like power timing system, set timing for what time the light to turn on and off, the problem is that while i know how to get real time and date from pc itself, i dont know how to link the timing setting to real time, maybe the printscreen can explain better? I would appreciate for a swift reply, thank you.
  10. Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segments will still not be visible - I just want to demonstrate the timing problem. However, the design fails to meet timing constraints as follows in attached pictures: Timing constraint failures in more detail, including the full source VHDL: Clock routing on the FPGA: The following is the .xdc constraints file (commented-out definitions are omitted): From what little I know about FPGA clock routing and resources, I understand this to be due to the high-frequency clock and associated logic being in different regions to each other, thus requiring the implementation run to route the clock signal through awkward paths; as a consequence, the total signal propagation time is such, that before the logic relevant to the current clock pulse is evaluated, the next clock front is already present. Am I correct in this thinking? And in either case, how can I fix the timing issues that Vivado warns about?
  11. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture of the the system I obtained at the end but this website would not let me. Any way, my system matches exactly the one in the tutorial. The validation passed, synthesis also passed ( although it gave me the same error the tutorial asked me to ignore, which I did). However, before running implementation I ran a "Report Timing Summary" from the Synthesized Design sub-menu, It gave me the several errors related to the oserdes_clk... To make sure these errors were not caused by something I may have entered wrong while creating the project, I decided to re-do the project starting from a blank slate, but the results were exactly the same in the new project. I tried to paste here an image with the errors but this website would not let me .... Anyway, the errors were Inter-clock paths / oserdes_clk to oserdes_clk / Hold -0.246ns (10 occurrences) Below is one of the Interclock paths that had the Hold timing error From: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK To: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST I think the error is due to a lack of one or more timing constraints. I suspect there might be an error with the board files associated to the Nexys-Video board, specifically related to the MIG7 and the DDR . I do not have enough knowledge of the system to be able to make the constraints myself. How could I solve these timing errors? Thanks