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Found 11 results

  1. Hi all, I am seeing an issue on multiple Digital Discovery devices, where the timing precision is off by over a percent (where I'd expect 10—100ppm, at least 2 orders of magnitude better). The problem can be seen most easily by having the device generate a simple 50% duty cycle clock on one of its output pins, e.g. 1 kHz. On two different Digital Discovery devices I tested, the scope reports a frequency of below 990 Hz. The signals otherwise look as expected (good level, stable, good edges) apart from the bad frequency behavior. I confirmed the measurement with a high-quality Ke
  2. I am working with an Arty design and I have noticed that while I have no intra-clock timing failures, I still have high severity warnings in the "check timing" portion of my timing summary related to not having constraints for input and output delay (no_input_delay and no_output_delay). Does digilent provide suggested timings for the on-board peripherals (like Ethernet and flash), or do I have to go through all the datasheets myself and estimate the trace delay? I found this thread from 2017, but the question was never resolved.
  3. Hello, my name is Caleb. I am a senior electrical engineering student at Northern Illinois University. I am using the Analog Discovery 2 in order to capture analog pixels sent from a sensor at 5MHz and then interpreting that data on the Raspberry Pi 4. I am running into questions with the timing of the logging function of the oscilloscope on the Analog Discovery. I have noticed that when I send multiple acquisitions at once I run into issues with the timing on the next acquisition. It seems that each acquisition comes in order, but there is a delay between the end of one and the beginning
  4. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem.
  5. I believe the clock latency is the total time it takes from the clock source to an end point. PFA Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture? Thanks Tip
  6. I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z] Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png Thanks
  7. Hello, I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning: [Timing 38-282] The design failed to meet the timing requirements. According to the Timing Report this warning refers to the
  8. Hello again! I'm trying to use the AD2 to act as both a signal source (wavegen1) and a measurement (scope1) device for the purpose of tracking conduction delay of the signal. Currently, I simply have the wavegen1 connected directly to scope1 with 3 cycles of a sine wave being put out. I am aware of the measure command to find the maximum on my scope1 but I was wondering if there was a way to find N (3 in my case) maximums AND find the corresponding times with respect to the timing of wavegen1? I plan to assume the timing of the wavegen1 is relatively accurate to my input frequency and c
  9. Hi fellow labview users, i need expert developing a system, what my system do is like power timing system, set timing for what time the light to turn on and off, the problem is that while i know how to get real time and date from pc itself, i dont know how to link the timing setting to real time, maybe the printscreen can explain better? I would appreciate for a swift reply, thank you.
  10. Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segm
  11. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture