Search the Community

Showing results for tags 'timing error'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. Dear Support, I am trying to implement a Microblaze in the Arty S7 with 50T FPGA board revision E. (yes Rev E not B). I instantiate GPIOs, Switches, LEDs, pushbuttons, UART and SPI at J7. I want to write c code to control the LEDs and talk to an SPI device. Attached is my implementation in picture format. The design verifies, synthesizes, and implements, but I get timing is negative. ISSUES 1. I am not sure how the GPIOs route from the block diagram to constraint file. I downloaded the constraint file, and uncomment the clock, and GPIO switches, etc...However, in the block diagram net names do not match the constraint file. I don't know how to map them In the case of the clock, I matched the Net CLK_12MHz in the block diagram to the constraint file, but for the GPIO, and others I am not sure I am doing this correctly. 2. Timing fails no matter if I change the CLOCK_OUT from 100MHz, 96MHz, 80MHz. Timing fails. HOW TO IMPLEMENT THE CONSTRAINT FILE TO BLOCK DIAGRAM...They should match no? Please advise how to fix timing, and how to map constraint file. I am sure I am not doing this right. I have watched numerous videos on implementation, and every implementation passes but they don't show how they setup other stuff. ## Clock Signals set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports CLK_12MHz]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports CLK_12MHz]; ## Switches set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0] set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2] set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3] ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Buttons set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1] set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2] set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3] ## USB-UART Interface set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in ## ChipKit SPI Header ## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time. set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck # Misc. ChipKit Ports #set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports RESET_N]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] # SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] Arty-S7-50-Rev-E-Master.xdc
  2. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture of the the system I obtained at the end but this website would not let me. Any way, my system matches exactly the one in the tutorial. The validation passed, synthesis also passed ( although it gave me the same error the tutorial asked me to ignore, which I did). However, before running implementation I ran a "Report Timing Summary" from the Synthesized Design sub-menu, It gave me the several errors related to the oserdes_clk... To make sure these errors were not caused by something I may have entered wrong while creating the project, I decided to re-do the project starting from a blank slate, but the results were exactly the same in the new project. I tried to paste here an image with the errors but this website would not let me .... Anyway, the errors were Inter-clock paths / oserdes_clk to oserdes_clk / Hold -0.246ns (10 occurrences) Below is one of the Interclock paths that had the Hold timing error From: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK To: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST I think the error is due to a lack of one or more timing constraints. I suspect there might be an error with the board files associated to the Nexys-Video board, specifically related to the MIG7 and the DDR . I do not have enough knowledge of the system to be able to make the constraints myself. How could I solve these timing errors? Thanks