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Showing results for tags 'tcl'.
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Hello all, Does someone know how can I instantiate the STARTUPE2 primitive in a project that uses only TCL? I am working to port from Arty A7 to Arty S7 and notice the constraint file has missing qspi_sck signal, then the following appears at the Arty S7 .xdc file ## Note: the SCK clock signal can be driven using the STARTUPE2 primitive But the project uses only tcl scripts. How can I workaround this? I found HDLC and Verilog examples under UG953 but I have limited experience on how to use them using TCL. Will appreciate any comments. Best,
Hello, I'm trying to build this demo: https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start and I have error while generating project (after run in console "source ./create_project.tcl") WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' Please help Any idea why it happens? I have: Windows 8.1 Vivado 2016.4 HLx WebPACK
Hello, I am trying to program a new zedboard and am having trouble programming the ps portion of the board with a bare metal application. I am following the tutorial outlined in the zynq book, in which you load some pre-written c code, which should blink some leds. Unfortunately, I keep getting stuck on the programming of the board. I select run as -> Launch On Hardware and it gets about 89% of the way though the program and then hangs on "Launching: ps7_init". Has anyone seen this before? I have tried it on both Ubuntu 16.04 and Windows 10, and both give the same problem. Furthermore, I am able to run "connect arm hw" in XMD console and it appears to work fine. I am also able to program just the PL fine as well through Vivado or SDK. I also don't think it is my header pin settings? I have them all set to gnd, which should be boot from JTAG. Other Info: Operating System: Tried on both Windows 10 and Ubuntu 16.04 (Virtual Machine) Vivado/SDK Version: Tried on both 2016.2 and 2016.4 ZedBoard: Latest Rev (D?) Power Source: Provided wall plug into US 120v 60hz
In order to figure out how to connect the on-board switches, buttons, and LEDs to Microblaze, I tried to follow the instructions in this Learnable. Sadly, the 'create_project.tcl' script seems out of date and can't be used to create a board design. I get the following error messages - ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.3> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.3>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script. ERROR: [BD 5-229] Please open or create a block design first. ERROR: [Common 17-39] 'get_bd_designs' failed due to earlier errors. while executing "get_bd_designs" invoked from within "set design_name [get_bd_designs]" (file "./create_project.tcl" line 106) Trying to run the entries in the create_project.tcl one at a time, or one at a time after creating and opening a block design, also failed with similar messages. Is there something obvious I'm missing? Could I get an updated version of the script?