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  1. Hello, there I have written a frequency divider.sv with SystemVerilog. But I have a problem about it. I use the following code to instantiate a two-level divider: divider CLK_DIV_1 ( .clk (clk), .rst (rst), .n (32'd100000000), .clkout (clk_0) ); divider CLK_DIV_2 ( .clk (clk_0), .rst (rst), .n (32'd4), .clkout (clk_1) ); The clk is 100MHZ, its period is 10ns. So the clk_0's period is 1s, and the clk_0's period is 4s. Then I connected clk_0 and clk_1 to two led lights