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Hello, my friends, i am new here and it is my first project. This project will be my BSC. I have to make next: 1. Make USB CAM interfacing on System Level using systemC... My diagrams are shown in the post. I need to capture the photo using a USB CAM. After that, the picture needs to be stored in some memory. After that the image processing logic (In my case, the logic needs to have the photo (stored in memory) as its input, the idea is just to decrease the photo size (pixels) and the output is the result (decreased size picture)), after that the result of processing needs to be stored in memory too. After that i have to choose... in easier way i will use some photo viewer to see the result, in more difficult way i will use HDMI in order to see my result on the HDMI enabled monitor. My plan is making it on System Level using coding, HLS,IP integrator, SDK for some software. 2.If SystemLevel work great i need to make it on RTL, IP level using pure HDL. I will use Vivado. I am not sure for now what i need to modify from SystemC to IP level (For now, i think just Image processing logic). 3.IP verification using QuestaSim. I have a question: 1. Has someone done something similar? Can you help me, like as give me some good literature or example (For now i am focusing on USB interfacing, i have been searching about this about few days, but without results..., I have read a book (SystemC "From Ground up")). 2. All suggestions are welcome Best regards!
Hi, I'm new to FPGAs and I have trouble finding documentation. In particular: How exactly VSync and HSync is handled for HDMI input? What can I assume about them? I'd like to create a AXI Master to store input in DDR. However I cannot find a reference for AXI4M_bus_port - how is timing handled for write_burst? Are there any guaranteed on ordering of stores through AXI Master to DDR? Matt