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Found 4 results

  1. Hi all! I am thinking of purchasing a genesys 2 Board which has a kintex-7 part on it. I have 3 FPGA boards (started with a small lattice board, then a medium altera board, then got a new laptop and a zynq board) and want to move up significantly from the Arty z-7 (which is still a great board) for some of my projects. The problem is, Im wondering if some FPGAs are too much for some computers with not enough resources? specifically Im worried about synthesis and implementation time. If you put the same design on different sized chips, does the larger chip take longer to synthe
  2. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_con
  3. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to
  4. I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly. However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole proj