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Found 9 results

  1. Hello, I am using Xilinx Vivado 2014.3.1 I'd like to use SRAM to DDR Component in my project. But I am newbie in VHDL, so I could just use the methods from this post. And finally, I had made a testbench which could write data into DDR memory and read data from the DDR. It's successful in Synthesis, Implementation and Generate bitstream. There are no critical wornings and errors. I want to use 7-segment to display the data that read from the DDR, however, it didn't work. This is my top module. Could someone help me with this issue? Thanks, Shaw test_ddr.v
  2. In my lab at work we are using a stash of old Nexys 2 boards for a prototype project. I need to verify the exact part number of the Hirose Fx2 connector, because it's highly embarrassing when you drop $20k on hardware and the cables don't mate. I have looked through the official docs without luck, and appreciate the help. It seems to me it's a FX2-100P-1.27DS. Correct? Many thanks!
  3. Hello, I am using Xilinx ISE 14.7 I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end. I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons. I started Translate and Map, Translate returned a lot of messages like: And Map returned: I found there http://www.xilinx.com/support/answers/34900.html a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the same). It removed these errors but now Map returned different error: I am using the ngc file from the /Netlist directory but i also tried to use files from /Source and i had the same problem. The solution for this issue on Xilinx Support tells me that i need to correct pin-out but I have downloaded official component so i think that it should work without any modifications. Could someone help me with this issue?
  4. Hello, I've been trying to implement the reference design described in wiki in Vivado 2015.2, but I get a timing violation in implementation. I follow the instructions step by step and I've even tried to change the implementation strategy to Explore, without any effects. As far as I can see the only difference is that in wiki the implementation was done in Vivado 2015.1. Has anybody else faced this problem? Thank you in advance! PS. I attach a screenshot of the timing summary in case it helps...
  5. DoogieTech

    Arty Board File

    Is there a .xml file available for vivado 14.4 and earlier for the Arty? Thanks!
  6. When will the Microblaze Base System Design Tutorial be updated? I've tried following the one for the NEXYS4 board but the MIG for the DDR3 on the ARTY is not quite the same as the one for the NEXYS4. There is an extra reference clock on the MIG block and the the resets pins are routed to the processor reset block instead of the MIG reset block. Thanks
  7. Hello! I am using Xilinx Vivado 2015.3 and Digilent Nexys 4 board. There is Cellular RAM on the board which has SRAM interface. What kind of IP do I need to make it work on MicroBlaze-based design? Example simple design would be greatly appreciated. Thanks, Alexander.
  8. I can confirm the problem with the Arty board definition being incorrect. I posted about this over at Avnet but there has been no response. I bought my board from them. I am attaching the ZIP file that I loaded into Vivado per the instructions. This is a pain because it's hard to get a MicroBlaze design going with an error like that. Any help is appreciated. Mike Harpe N4PLE arty.zip
  9. The ARTY GPIO demo is set up for the XC7A15T, but the actual device that has been fitted is the XC7A35T. This error should be corrected.