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When sweeping frequency in the network or impedance analyzers, the default number of samples is 100, but this usually results in awkward values, as it corresponds to 99 steps (fencepost error). It would be better to make the default be 101 samples. It might also be nice to have a way of setting the step size, rather than the number of samples. For linear spacing, this is just a value in Hz (for example, 10Hz–100Hz in steps of 1Hz is 91 samples). For logarithmic spacing, specifying a ratio is awkward, but steps/decade is simple. For example, the 1 kHz–1 MHz at 50 steps/decade is 151 samples). I'm usually more interested in controlling the steps/decade than the total number of samples.
Why does the impedance analyzer only allow 10Ω, 100Ω, 1kΩ, 10kΩ, 100kΩ, and 1MΩ reference resistors? I might have a precision 510Ω resistor that I want to use for a reference. Or, as happened for me today, I might want to use a 1Ω resistor as a reference (I was trying to determine the saturation current for an inductor, so I needed a large DC current, plus a small signal to measure impedance with.) I added an external transistor to provide gain from the function generator, but the 10Ω constraint meant that I couldn't raise the current much without hitting voltage limits. (I'll have to use the network analyzer and do my own fitting, rather defeating the advantage of the impedance analyzer) I found the impedance analyzer a bit non-intuitive to use and almost completely undocumented. It is a bit annoying that compensation needs to be redone any time the sweep is changed, and there there is no way to store a number of different compensation sets, switching between them as needed. I was also wondering why the impedance analyzer used a shared ground, rather than taking advantage of having differential inputs to measure the voltage across the resistor and the unknown impedance separately. Using the differential channels, one can have a larger difference in |Z| between the reference and the unknown, since you don't have to compare R with R+Z, but only with Z.
Hi! I'm just playing around with a low cost board that has HDMI input and output on it. It would make a very valuable but low cost addition on the next Basys and or Nexys model, given that analogue VGA displays are very pretty soon going to disappear. From the engineering point of view, Implementing DVI-D is a great way to experience the "pleasure" of high speed serial communications. From the student/hobbyist point of view, playing with camera modules and image processing algorithms with 8-bit or 12-bit VGA output is quite lame. From a purely aesthetic point of view, 24-bit colour images are so much nicer than low colour depths. From a cost point of view, it is one connector and maybe a few passives, and 8 pins on the FPGA. The only downside is that FPGAs don't have oodles of block RAM, and most low-cost high-capacity memory solutions (e.g. SDRAM) are relatively low bandwidth. This forces you have to process the data as it flows through the FPGA rather than bouncing frames in and out of memory of a frame buffer. Mike