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  1. Hello, I am using Xilinx Vivado 2014.3.1 I'd like to use SRAM to DDR Component in my project. But I am newbie in VHDL, so I could just use the methods from this post. And finally, I had made a testbench which could write data into DDR memory and read data from the DDR. It's successful in Synthesis, Implementation and Generate bitstream. There are no critical wornings and errors. I want to use 7-segment to display the data that read from the DDR, however, it didn't work. This is my top module. Could someone help me with this issue? Thanks, Shaw test_dd