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Found 7 results

  1. How to access SRAM on Cmod A7-35T in VHDL,Verilog? is there any reference design that includes SRAM interface?
  2. Hi, I have a problem setting heap and stack sizes for my application on a CMOD A7 35T. Briefly, through the linker script, I set heap and stack sizes to be placed into the axi_emc_0_S_AXI_MEM0_BASEADDR (64 MB), the emc controller of the onboard SRAM. So a bootloader copies the program from flash to this memory. First of all, I set the emc to 64 MB in the VIvado address editor, but the size of the onboard SRAM is 512kB. What does it mean? Is the actual available size of the memory 64MB or 512KB? Moreover, if I increase the two sizes, heap and stack, from 800kB to 1 or 2 or 4 MB the pr
  3. Hello! I am using Xilinx Vivado 2015.3 and Digilent Nexys 4 board. There is Cellular RAM on the board which has SRAM interface. What kind of IP do I need to make it work on MicroBlaze-based design? Example simple design would be greatly appreciated. Thanks, Alexander.
  4. I'm about to play with the Nexys4 DDR "SRAM to DDR" component, but I've never used a MIG or a pre-existing netlist before. The instructions say "Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project." Can someone help me with an explanation on how to do this?! I'm using Vivado 2015.1. Thanks all! Warren
  5. Hi all, I am creating a custom CPU on the Nexys 4 DDR. At 100 MHz system clock, it executes commands at about 20 MIPS on average. I used async SRAM in past, this was a piece of cake as the SRAM was always faster than my CPU. But now, being on the Nexys 4 DDR, I'd like to leverage the on board DDR RAM. Having a look at Mihaita Nagy's DDR to SRAM component (link: I was a bit surprised: On the reference page you can read, that an async. read operation of a single data word takes 210ns. Is this realistic or maybe a typo? 210ns means that the max r
  6. Now that I've got one CPU working using block RAM, my next project is to design a CPU which uses the SRAM to DDR component on the Nexys4 DDR board. I'd like to do some behavioral and timing simulation of the SRAM first, using GHDL and Vivado. Is there a VHDL model for this SRAM, or can somebody point me at a model which I could adapt? I did look on the Digilent VHDL components page but I didn't see it there. I have found several SRAM models, but none seem to deal with the timing delay or the upper/lower byte input. Slightly off-topic (becau
  7. Hi guys, I want to write instruction into nexys4 SRAM to control my small CPU project. What I thought is to use JTAG. But I don't know where to find the USB control interface for nexys4. Does anyone could give me a piece of advice on that? Best Jay.