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  1. Hi, I'm trying to read the Configuration Flash of the Nexys4DDR. I need to achieve a relatively high speed. Here is a short summary of what I'm trying to do: My design will be controlled by an external master and there is no way to delay the masters request. The start address is latched first. After that I have about 1 us until the first read request will be applied. The subsequent reads will occur in a burst with a read cycle time of about 350 ns. Each read must deliver 16 bits of data to the master. I've been thinking about the QSPI-Flash as some kind of boot rom. And now I'm trying out if this is possible. With some combination of a high Frequency, the DDR and Quad I/O feature of the S25FL128S this could be done I believe. For the first step I got the SPI-Interface itself working using the Digilent SPI_If from the Nexys4DdrUserDemo. The SPI clock is output using the STARTUPE2. I could already read the device ID and some data successfully at 25 MHz. But at 50 MHz I'm reading garbage. Then I tested the maximum Configuration Rate (4 bit width) to find out if it is only a problem of my design. The Artix7 should be able to output a 100 MHz clock on the CCLK-Pin (FMCCK). The QSPI Flash should handle 133 MHz. But for me the maximum Configuration Rate is 40. Setting the CR to 50 will cause the FPGA to never load from SPI. Also when I attach my oscilloscope to the clock pin, the configuration at CR40 fails. So, my questions are: - What is (or should be) the maximum clock frequency of the Nexys4DDR QSPI design? - Is the FMCCK = 100 MHz only valid for configuration or is this also the maximum clock for the user design? - Do I have to constraint some attributes of the QSPI I/Os to achive a high clock? - Can this be done with "normal" logic or do I have to deal with something like SERDES? I'm using Vivado 2015.4 and have applied the contraints for "Clock signal" and "Quad SPI Flash" from the Nexys4DDR_Master.xdc from Digilent. Regards, Jago