Search the Community

Showing results for tags 'spi'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Calendars

  • Community Calendar

Found 52 results

  1. SPI_SLAVE_intr_example not working

    Hi all, I am working with zybo zync 7010. i am trying to build spi slave using quad spi using sdk example program. but the data is not received. program hangs on at while (TransferInProgress==TRUE) and will never come out of the loop. please help me out.
  2. PMOD DA4

    Hello, I am trying to use the pmod DA4 with my Arty S750 board. I'm aware that Digilent does not offer an IP for interacting with the Pmod, so I took it upon myself to design one. Anyways, things seemed to be going well until I actually tested the DA4. I know that the DA4 uses SPI to communicate, so I programmed the IP to communicate that way, and it does (outputs from the pmod connector correctly seen on an oscilloscope), but every time I connect it to the DAC I can't get much of anything to come out of the channels. I've read through the AD5628 reference manual, but a few things were ambiguous to me. First the commands on table 9. I don't really understand the difference between writing to the register (command 0) and writing to the DAC channel (command 3), and which I should be using for my project. And second, I plan on using an internal voltage, and it says that setting up the internal voltage is the first step. As I have it now, it's the first thing my program does and I'm afraid that the DAC is unable to read this input (maybe I should add a brief delay? I saw a brief delay in the "simon says" code). I know it's been a long post, but any answers or insights on the DA4 or any other part of my post is much appreciated. Thanks, Gill
  3. I'm having trouble getting the SPI1 port working as a slave on the Cmod board. It works fine as a master talking to an Arduino Mini Pro configured as a slave, but not vise versa. I verified that the Arduino Mini configured as a master is working, but I never receive anything in the SPI1BUF on the Cmod. I have tried setting SPI1CON to 0x8000 and 0x8080, but neither worked. Does anyone have sample code that works as a spi slave?
  4. I am new user of Waveforms 2015 and the Digital Discovery. I want to generate SPI signal and DIOs, to read from multiplexed-CH ADC. According to "Help" on WaveForms, DIO can be set using "DIO." in script for Protocol-SPI. (Help -> Protocol -> 2. SPI -> about Custom mode -> " DIO.: Lets you set(the ones are not declared as SPI signal) and red the digital pins." ) but I can't find its description. So, could I have the example how to use "DIO." in script for Protocol-SPI ? * I'm using WaveForms Ver:3.7.5 32-bit Qt5.6.3 Windows7. Thanks,
  5. SPI Sniffing with WF SDK

    Hello, I've got a question on how to sniff SPI data using Analog Discovery with the WaveForms SDK. The following example uses "sync record" which only stores samples on SPI clock or select (rising) edge. This lets you capture SPI data with an average bit rate of around 2MHz. SPI bursts of up to 40MHz are supported but the average rate needs to be lower. DigitalIn_Spi_Spy.py
  6. FPGA SPI transfer timed out

    Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torvalds repository (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) program that I'm using shows one of two things: 1. Either the result is always an error of "SPI transfer timed out" 2. or the value in rx is the same as in tx. That is, even though the SAMA slave is demonstrably (via oscilloscope) returning something else, all the RX buffer gets is the same as was sent via the TX buffer. In fact, I can even disconnect the header that plugs the master to the slave, and this behavior becomes no different. The difference between these two results is simply a matter of removing the 1050th line in drivers/spi/spi.c when building the kernel. It's the call to wait_for_completion_timeout() in the function static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *msg). What I get from this is basically that the spi-xilinx.c driver does not know where to look for the output from the slave (MISO), and it either waits eternally for that output (if the call to wait_for_completion is left intact) OR it doesn't care to look for the data and just fills the rx buffer with the tx buffer. Now I have a very limited understanding of hardware and driver programming, so I'm basically like a blind man in the dark here. I'm adding printk() statements to spi-xilinx.c and spi.c everywhere, and checking their results with dmesg and there's just nothing enlightening (I'm using PetaLinux, and the devices all show up correctly in /dev and /sys). I'm hoping someone more experienced can shine a light on what I'm doing wrong here, or at least point me in the right direction. Attached is my device tree file, plus a screenshot of the hardware design. (the relevant node in the DT is highlighted below) amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "simple-bus"; ranges; axi_quad_spi@41e00000 { bits-per-word = <0x8>; compatible = "xlnx,xps-spi-2.00.a"; clock-names = "axi_clk", "spi_clk"; clocks = <0x1 0xf>, <0x1 0xf>; fifo-size = <0x10>; interrupt-parent = <0x4>; interrupts = <0x0 0x1d 0x1>; num-cs = <0x1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; xlnx,spi-mode = <0x0>; spidev@0 { compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x17d7840>; }; }; }; goodVersion1.dts
  7. CMOD A7: accessing the SPI Flash

    I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz
  8. Zynq SPI timed out

    Dear All, Me and a colleague of mine are facing an SPI timeout issue on a Zynq. We already posted the issue in the Xilinx forum: https://forums.xilinx.com/t5/Embedded-Linux/SPI-transfer-timeout/td-p/833550 but we did not receive any answer, yet. So I would like to ask your help. I am trying to use a TFT LCD screen with the Digilent Artyz7, exploiting the frame buffer. I created a project on Vivado that exports the Zynq PS SPI interface through EMIO. I have already deployed the linux-digilent kernel (v4.4.0) on the Zynq and I am able to see the SPI peripheral under /sys/class/spi_master/spi2.0 (the device tree has been generated using SDK). Thus, as soon as I try to insert the kernel module for the frame buffer support, I get the following error: spi2.0: SPI transfer timed out I attach the images from the logic analyzer: The kernel module of the frame buffer sends the data correctly through the SPI interface before going to timeout state. Any ideas or suggestions regarding this issue? Thanks a lot. Best Regards, Enrico
  9. SPI under Logic

    Hello, I just received my AD2, and I really like it! I like the WG and the scope, and while it took me a little while to figure out the Protocol analyzer, it does a pretty good job showing the data. However, at first glance, the SPI protocol handler under the logic analyzer is somewhat limited because it only handles one channel. One could capture four signals by using the logic analyzer and doing the work manually, but I would like to be able to handle all four (or 6) SPI channels in the logic analyzer, too. I have an MCP3208 which requires a command in the first 10 bits, and then in the next 14 bits returns the data on the MISO pin. Is there any way to do this in the logic analyzer? Thanks Matt Gessner
  10. Usign multiple PmodACL with Zedboard by SPI

    Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  11. I desperately want to connect three devices to a Raspberry Pi3 that has a single Pmod HAT Adapter fitted to it. The devices are all SPI types: Pmod AD1 Pmod ISNS20 Pmod TC1 I can only run 2x devices since ports JA(A) and JB(A) both support SPI, but JC(A) does not. Is stacking of Pmod HAT Adapters allowed or can I connect an SPI device directly to the open GPIO pins? I would greatly appreciate any advice! Even if NOPE is an answer...
  12. I want to capture UART data and SPI data at the same time in the Logic analyzer of Analog Discovery 2. UART baud is 115.2kHz and SPI is at 8Mhz. when i increase the sample rate, UART data is not captured. and without increasing the sample rate i can not capture SPI data. what is the optimal setting to capture both low frequency and high frequency signals at the same time?
  13. HS2 Programming Cable. Multiple Instances

    I have a system where I'm using 2 HS2 cables. One is used for SPI control and the other for Jtag. For my SPI interface, I have written a DLL using the ADEPT2 SDK, that allows me to specify the serial number of teh device to connect for SPI. Unfortunately both devices enumerate as device name "jtagHs2" and If I start my Xilinx Viivado Hardware manager before my SPI interface, the Vivado is taking over the device I want to use for SPI. If I start my spi interface first then vivado correctly picks up the HS2 I want to use for JTAG. Is there a way to prevent this, for example can I change the name "jtagHS2" in my SPI interface eeprom? Thanks, Patrick
  14. NEED HELP WITH R-PI AND Pmod ACL2

    I am very new to Raspberry pi and I need help regarding my R-Pi and Pmod ACL2 I would just like to test the functionality of the SPI connection and that's it I am not allowed to install any software I should just use the configure terminal I have installed the spi-dev on my R-Pi and I can't seem to find the ACL2 I'm sure I have connected them correctly Pls help Thanks in Advance
  15. Hello, I am attempting to communicate to a Pmod RF2: IEEE 802.15 RF Transceiver with a Basys3 board using the SPI protocol in VHDL. The microchip on the pmod is the MRF24J40. How do I identify the address of the MRF24J40? To my understanding, if I want to write/read a memory location on the MRF24J40, I need to send the address followed by the address of the specific memory location on the MRF24J40. Is it written on the microchip itself? The master and slave SPI modules that I am attempting to use are linked to this post. The documentation for the master and slave links are below. The specification sheets for the pmod and MRF24J40 are included as well. Master: https://eewiki.net/pages/viewpage.action?pageId=4096096#SerialPeripheralInterface(SPI)Master(VHDL)-Transactions Slave: https://eewiki.net/pages/viewpage.action?pageId=7569477 Pmod: https://www.digilentinc.com/Pmods/Digilent-Pmod_ Interface_Specification.pdf MRF24J40: http://ww1.microchip.com/downloads/en/DeviceDoc/39776C.pdf Thank you. spi_slave.vhd spi_master.vhd
  16. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  17. PmodCLS - missing character on SPI

    Hi, I'm trying to use my PmodCLS (rev. E) with an STM32F723E-DISCO board. I connected it to the SPI port (J1 connector) and configured the SPI with CPOL=1 CPHA=0. I configured the module using the following commands: write("\x1b[j", 3); write("\x1b[0h", 4); write("\x1b[0c", 4); write("\x1b[0;0H", 6); Then I'm sending some ASCII string. The problem is that the last character does not appear on the display. I investigated it for some time and found out that it concerns also the commands. It looks like the last character from the previous transaction is received by the Pmod at the beginning of the next transaction. For example, if I send "ABC" I can see only "AB" on the LCD. But when I send "DEF" after that I can see "ABCDE". I checked the waveforms on the scope but all the signals look fine and all the data is transmitted from the STM32 microcontroller's SPI. To make sure that it is not the SPI configuration I also checked other SPI modes but changing CPHA to 1 has the same effect, and changing CPOL to 0 causes the module to display trash because some bits from the beginning of each transaction are lost. I suspect that it is some problem with my configuration but I have no more ideas what can I change to make it work fine. Thanks for any help, Chris
  18. arty microblaze quad spi

    Hello, I'm having some issues with multiple (16bit) transactions while holding slave select low. I'm using the example master polling spi code from the xilinx SDK, and have manual slave select working where it holds the SS line low while performing the multiple transactions, and once finish it goes high again. My issue is that i'm trying to make a simple slave which can write to a register continuously if it receives a write command from the master, and then if a read command is sent from the master, the slave will send back whatever is in the designated register requested by the master. Is the data transmit register also a double buffer? My main objectve is to receive the read command, and start transferring the data on the next group of SCK pulses but right now it seems to be delayed by two transactions. The image attached shows more of what i'm trying to accomplish. the high bit of the 16 bits is a read/write(1 is write, 0 is read) command, and the lower bits are a register address. so the final result of the first 3 transactions should result in register 5 having the value (0x8009), which it does, but when the next transfer happens, the 0x0005 command should be indicating a read of register 5 and output on the miso line 0x8009 on the 2nd transaction (i.e. when MOSI is 0x0007 i want MISO to have 0x8009). Also this is my current code: /***************************** Include Files **********************************/ #include "xparameters.h" #include "xstatus.h" #include "xspi_l.h" #include "xil_printf.h" /************************** Constant Definitions ******************************/ /* * The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily * change all the needed parameters in one place. */ #define SPI_BASEADDR XPAR_SPI_0_BASEADDR /**************************** Type Definitions ********************************/ /***************** Macros (Inline Functions) Definitions **********************/ /************************** Function Prototypes *******************************/ /************************** Variable Definitions ******************************/ /* * This is the size of the buffer to be transmitted/received in this example. */ #define BUFFER_SIZE 16 /* * The buffer used for Transmission/Reception of the SPI test data */ u16 Buffer[BUFFER_SIZE]; /* * This buffer is used to simulate a register bank. */ u16 regBank[64]; /******************************************************************************/ /** * This function is the main function of the SPI Low Level example. * * @param None * * @return XST_SUCCESS to indicate success, else XST_FAILURE to indicate * Failure. * * @note None * *******************************************************************************/ int main(void) { //int transferCounter = 0; u32 BaseAddress = SPI_BASEADDR; u16 addressMask = 0; u32 StatusReg = 0; u32 NumBytesRcvd = 0; u32 NumBytesSent = 0; u8 addressFlag = 0; u16 tester = 0; //Enable GIER XSpi_WriteReg(BaseAddress, XSP_DGIER_OFFSET, 0x0/*XSP_GINTR_ENABLE_MASK*/); for(int i = 0; i < 65; i++){ regBank = 0xBEEF; } for(int i = 0; i < BUFFER_SIZE; i++){ Buffer = 0x0; } //Configure IPIER XSpi_WriteReg(BaseAddress, XSP_IIER_OFFSET, 0x0 /*XSP_INTR_SLAVE_MODE_MASK | XSP_INTR_RX_OVERRUN_MASK | XSP_INTR_RX_FULL_MASK | XSP_INTR_TX_UNDERRUN_MASK | XSP_INTR_TX_EMPTY_MASK | XSP_INTR_SLAVE_MODE_FAULT_MASK | XSP_INTR_MODE_FAULT_MASK*/); //Configure SPICR XSpi_WriteReg(BaseAddress, XSP_CR_OFFSET, XSP_CR_ENABLE_MASK); //Write data to the SPI DTR XSpi_WriteReg(BaseAddress, XSP_DTR_OFFSET, 0xDEAD); xil_printf("setup registers hi\r\n"); while(1){ if(NumBytesRcvd == 4){ for(int i = 0; i < BUFFER_SIZE; i++){ xil_printf("buffer: 0x%x regBank: 0x%x addressmask: %d\r\n", Buffer, regBank , addressMask); } } NumBytesSent = 0; NumBytesRcvd = 0; addressMask = 0; if((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_SLAVE_MODE_MASK) == 0){ /* * Fill up the transmitter with data, assuming the receiver can hold * the same amount of data. */ while ((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK) == 0) { XSpi_WriteReg((BaseAddress), XSP_DTR_OFFSET, Buffer[NumBytesSent++]); } /* * Wait for the transmit FIFO to transition to empty before checking * the receive FIFO, this prevents a fast processor from seeing the * receive FIFO as empty */ while (!(XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_TX_EMPTY_MASK)); /* * Transmitter is full, now receive the data just looped back until * the receiver is empty. */ while ((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_RX_EMPTY_MASK) == 0) { Buffer[NumBytesRcvd++] = XSpi_ReadReg((BaseAddress), XSP_DRR_OFFSET); } if(Buffer[0] & 0x8000){ addressMask = Buffer[0] & 0x00FF; regBank[addressMask] = Buffer[0]; }else{ addressMask = Buffer[0] & 0x00FF; XSpi_WriteReg((BaseAddress), XSP_DTR_OFFSET, regBank[addressMask]); } } } for(int i = 0; i < BUFFER_SIZE; i++){ xil_printf("buffer: 0x%x regBank: 0x%x addressmask: %d\r\n", Buffer, regBank , addressMask); } } Greatly appreciate the help! Nystflame
  19. Arty Microblaze SPI J6 Header

    Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design. I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers). Regards, Nystflame
  20. SPI Interface -> Quad-SPI Flash.

    hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  21. Hi, I have a SPI slave design with 4-mode and can be auto change by custom script, after updating to 3.6.8, the POL & PHA seems be locked on the upper settings, only the POL & PHA value on the upper settings are valid, even I un-check the "Settings". How can I solve it? thanks.
  22. SPI sensor script ReadWrite not working (3.6.8)

    In Waveforms 2015 3.6.8 on a Mac OS 10.11.6 with an Analog Discovery 2, I am not able to get the SPI sensor scripts to work. I'm having no trouble with Master or Custom scripts, but with the Sensor scripts the ReadWrite() commands always return an array of zeros, even if I'm not in Debug mode. (I tried starting from a fresh run of Waveforms, to make sure that the debug setting was not just being excessively sticky.) Can anyone else duplicate this behavior? Or is it just me? Incidentally, the documentation for the protocol instrument and the scripts is woefully inadequate—I had to figure out how things worked by trial and error, because of the extreme lack of information in the documentation.
  23. Hello, I am trying to avoid all of those SPI commands with higher level abstractions. The low-level example seems to help, but it is incomplete. It doesn't show how to setup or toggle the slave select lines. I presume this is done automatically, but I want manual control. I cannot find information on MicroBlaze registers. For example, let's look at XSpi_SetSlaveSelect. This is all I could find: file:///C:/Xilinx/SDK/2016.2/data/embeddedsw/XilinxProcessorIPLib/drivers/spi_v4_2/doc/html/api/group__spi__v4__1.html#ga162523a3e9b29f063701db303ac8cf17 . It's not very clear, or correct. Let me explain. I only have one slave: here is my constraint file for the SPI signals: set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { spi_0_ss_io[0] }]; #CS #IO_L5N_T0_D07_14 Sch=ja[1] set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { spi_0_io0_io }]; #MOSI #IO_L4N_T0_D05_14 Sch=ja[2] set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { spi_0_io1_io }]; #MISO #IO_L9P_T1_DQS_14 Sch=ja[3] set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { spi_0_sck_io }]; #SCK #IO_L8P_T1_D11_14 Sch=ja[4] I am using the CMOD-A7 module.These are pins on the PMOD connector. My slave select is on JA-1, as you can see. Let me demonstrate with a code snippet: while(1) { XSpi_SetSlaveSelect ( XPAR_SPI_0_BASEADDR, (u32)0x01); // This should have set my SS[0] pin to 1. It doesn't. wait a time delay XSpi_SetSlaveSelect ( XPAR_SPI_0_BASEADDR, (u32)0x00); // This should have set my SS[0] pin to 0. It's always 0, so I don't know if this worked or not. wait a time delay } This should just toggle the pin, but it doesn't. Can someone please provide a simple SPI example that is only 1 level deep (in file hierarchy)? Please include example that sets up the SPI to use the correct slave pin, and then toggles it. I included my main project file. This was originally from the Polled SPI example project, "xspi_polled_example.c", so everything else was generated by SDK. If you create a basic project with an SPI port, then you can just replace the contents of that file with that of this file and it will compile. Thank you, Richard V Temp.c
  24. Implementation SPI basys3

    Hi, I need your help please, actually I am work in an arduino communication with FPGA (Basys3), but i have a problem with the implementation, can you help me? VHDL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SPI_rx3_top is Port ( SCK : in STD_LOGIC; -- SPI input clock DATA : in STD_LOGIC; -- SPI serial data input CS : in STD_LOGIC; -- chip select input (active low) led : out STD_LOGIC_VECTOR (7 downto 0) := X"FF"); end SPI_rx3_top; architecture Behavioral of SPI_rx3_top is signal dat_reg : STD_LOGIC_VECTOR (7 downto 0); begin process (SCK) begin if (SCK'event and SCK = '1') then -- rising edge of SCK if (CS = '0') then -- SPI CS must be selected -- shift serial data into dat_reg on each rising edge -- of SCK, MSB first dat_reg <= dat_reg(6 downto 0) & DATA; end if; end if; end process; process (CS) begin if (CS'event and CS = '1') then -- update LEDs with new data on rising edge of CS led <= not dat_reg; end if; end process; end Behavioral; XDC: ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {CS}] set_property IOSTANDARD LVCMOS33 [get_ports {CS}] ##Sch name = JB2 set_property PACKAGE_PIN A16 [get_ports {DATA}] set_property IOSTANDARD LVCMOS33 [get_ports {DATA}] ##Sch name = JB3 set_property PACKAGE_PIN B15 [get_ports {SCK}] set_property IOSTANDARD LVCMOS33 [get_ports {SCK}] Warnings: [Place 30-876] Port 'SCK' is assigned to PACKAGE_PIN 'B15' which can only be used as the N side of a differential clock input. Please use the following constraint(s) to pass this DRC check: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SCK_IBUF}] [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances
  25. SPI - Arduino to Basys 3

    Arduino is the SPI Master and therefore provides the clock, SPICLK through a PMOD. How do I receive the clock in a good way on the FPGA? Vivado does not approve of checking rising_edge(SPICLK) so I though I'd put a clock buffer or something in between (not that I know why or what they do but it sounds like a good idea). At some point Vivado told me to add "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SPICLK_IBUF}]" to the constraints file, but I still got warnings and it didn't recommend I proceed. If I have the top level SPICLK connected to an IBUF_IBUFDISABLE with the disable line connected to the slave select (SS) line, I get this warning: [DRC 23-20] Rule violation (CKLD-2) Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads - Clock net spi_buf is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): IBUF_IBUFDISABLE_inst/O If I have the top level SPICLK connected to an IBUF_IBUFDISABLE and that into a BUFGCE, with the disable line connected to the slave select (SS) line and the inverse of SS into the CE, I get this warning: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. IBUF_IBUFDISABLE_inst (IBUF_IBUFDISABLE.O) is locked to IOB_X0Y25 and BUFGCE_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 Roughly the same warning was issued with just the BUFGCE. I know there are other ways of polling the input clock from the arduino and treating it as normal signal but I want to do it the "proper" way.