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Found 38 results

  1. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  2. Hello, I am attempting to communicate to a Pmod RF2: IEEE 802.15 RF Transceiver with a Basys3 board using the SPI protocol in VHDL. The microchip on the pmod is the MRF24J40. How do I identify the address of the MRF24J40? To my understanding, if I want to write/read a memory location on the MRF24J40, I need to send the address followed by the address of the specific memory location on the MRF24J40. Is it written on the microchip itself? The master and slave SPI modules that I am attempting to use are linked to this post. The documentation for the master and slave links are below. The specification sheets for the pmod and MRF24J40 are included as well. Master: https://eewiki.net/pages/viewpage.action?pageId=4096096#SerialPeripheralInterface(SPI)Master(VHDL)-Transactions Slave: https://eewiki.net/pages/viewpage.action?pageId=7569477 Pmod: https://www.digilentinc.com/Pmods/Digilent-Pmod_ Interface_Specification.pdf MRF24J40: http://ww1.microchip.com/downloads/en/DeviceDoc/39776C.pdf Thank you. spi_slave.vhd spi_master.vhd
  3. PmodCLS - missing character on SPI

    Hi, I'm trying to use my PmodCLS (rev. E) with an STM32F723E-DISCO board. I connected it to the SPI port (J1 connector) and configured the SPI with CPOL=1 CPHA=0. I configured the module using the following commands: write("\x1b[j", 3); write("\x1b[0h", 4); write("\x1b[0c", 4); write("\x1b[0;0H", 6); Then I'm sending some ASCII string. The problem is that the last character does not appear on the display. I investigated it for some time and found out that it concerns also the commands. It looks like the last character from the previous transaction is received by the Pmod at the beginning of the next transaction. For example, if I send "ABC" I can see only "AB" on the LCD. But when I send "DEF" after that I can see "ABCDE". I checked the waveforms on the scope but all the signals look fine and all the data is transmitted from the STM32 microcontroller's SPI. To make sure that it is not the SPI configuration I also checked other SPI modes but changing CPHA to 1 has the same effect, and changing CPOL to 0 causes the module to display trash because some bits from the beginning of each transaction are lost. I suspect that it is some problem with my configuration but I have no more ideas what can I change to make it work fine. Thanks for any help, Chris
  4. arty microblaze quad spi

    Hello, I'm having some issues with multiple (16bit) transactions while holding slave select low. I'm using the example master polling spi code from the xilinx SDK, and have manual slave select working where it holds the SS line low while performing the multiple transactions, and once finish it goes high again. My issue is that i'm trying to make a simple slave which can write to a register continuously if it receives a write command from the master, and then if a read command is sent from the master, the slave will send back whatever is in the designated register requested by the master. Is the data transmit register also a double buffer? My main objectve is to receive the read command, and start transferring the data on the next group of SCK pulses but right now it seems to be delayed by two transactions. The image attached shows more of what i'm trying to accomplish. the high bit of the 16 bits is a read/write(1 is write, 0 is read) command, and the lower bits are a register address. so the final result of the first 3 transactions should result in register 5 having the value (0x8009), which it does, but when the next transfer happens, the 0x0005 command should be indicating a read of register 5 and output on the miso line 0x8009 on the 2nd transaction (i.e. when MOSI is 0x0007 i want MISO to have 0x8009). Also this is my current code: /***************************** Include Files **********************************/ #include "xparameters.h" #include "xstatus.h" #include "xspi_l.h" #include "xil_printf.h" /************************** Constant Definitions ******************************/ /* * The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily * change all the needed parameters in one place. */ #define SPI_BASEADDR XPAR_SPI_0_BASEADDR /**************************** Type Definitions ********************************/ /***************** Macros (Inline Functions) Definitions **********************/ /************************** Function Prototypes *******************************/ /************************** Variable Definitions ******************************/ /* * This is the size of the buffer to be transmitted/received in this example. */ #define BUFFER_SIZE 16 /* * The buffer used for Transmission/Reception of the SPI test data */ u16 Buffer[BUFFER_SIZE]; /* * This buffer is used to simulate a register bank. */ u16 regBank[64]; /******************************************************************************/ /** * This function is the main function of the SPI Low Level example. * * @param None * * @return XST_SUCCESS to indicate success, else XST_FAILURE to indicate * Failure. * * @note None * *******************************************************************************/ int main(void) { //int transferCounter = 0; u32 BaseAddress = SPI_BASEADDR; u16 addressMask = 0; u32 StatusReg = 0; u32 NumBytesRcvd = 0; u32 NumBytesSent = 0; u8 addressFlag = 0; u16 tester = 0; //Enable GIER XSpi_WriteReg(BaseAddress, XSP_DGIER_OFFSET, 0x0/*XSP_GINTR_ENABLE_MASK*/); for(int i = 0; i < 65; i++){ regBank = 0xBEEF; } for(int i = 0; i < BUFFER_SIZE; i++){ Buffer = 0x0; } //Configure IPIER XSpi_WriteReg(BaseAddress, XSP_IIER_OFFSET, 0x0 /*XSP_INTR_SLAVE_MODE_MASK | XSP_INTR_RX_OVERRUN_MASK | XSP_INTR_RX_FULL_MASK | XSP_INTR_TX_UNDERRUN_MASK | XSP_INTR_TX_EMPTY_MASK | XSP_INTR_SLAVE_MODE_FAULT_MASK | XSP_INTR_MODE_FAULT_MASK*/); //Configure SPICR XSpi_WriteReg(BaseAddress, XSP_CR_OFFSET, XSP_CR_ENABLE_MASK); //Write data to the SPI DTR XSpi_WriteReg(BaseAddress, XSP_DTR_OFFSET, 0xDEAD); xil_printf("setup registers hi\r\n"); while(1){ if(NumBytesRcvd == 4){ for(int i = 0; i < BUFFER_SIZE; i++){ xil_printf("buffer: 0x%x regBank: 0x%x addressmask: %d\r\n", Buffer, regBank , addressMask); } } NumBytesSent = 0; NumBytesRcvd = 0; addressMask = 0; if((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_SLAVE_MODE_MASK) == 0){ /* * Fill up the transmitter with data, assuming the receiver can hold * the same amount of data. */ while ((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK) == 0) { XSpi_WriteReg((BaseAddress), XSP_DTR_OFFSET, Buffer[NumBytesSent++]); } /* * Wait for the transmit FIFO to transition to empty before checking * the receive FIFO, this prevents a fast processor from seeing the * receive FIFO as empty */ while (!(XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_TX_EMPTY_MASK)); /* * Transmitter is full, now receive the data just looped back until * the receiver is empty. */ while ((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_RX_EMPTY_MASK) == 0) { Buffer[NumBytesRcvd++] = XSpi_ReadReg((BaseAddress), XSP_DRR_OFFSET); } if(Buffer[0] & 0x8000){ addressMask = Buffer[0] & 0x00FF; regBank[addressMask] = Buffer[0]; }else{ addressMask = Buffer[0] & 0x00FF; XSpi_WriteReg((BaseAddress), XSP_DTR_OFFSET, regBank[addressMask]); } } } for(int i = 0; i < BUFFER_SIZE; i++){ xil_printf("buffer: 0x%x regBank: 0x%x addressmask: %d\r\n", Buffer, regBank , addressMask); } } Greatly appreciate the help! Nystflame
  5. Arty Microblaze SPI J6 Header

    Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design. I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers). Regards, Nystflame
  6. SPI Interface -> Quad-SPI Flash.

    hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  7. SPI sensor script ReadWrite not working (3.6.8)

    In Waveforms 2015 3.6.8 on a Mac OS 10.11.6 with an Analog Discovery 2, I am not able to get the SPI sensor scripts to work. I'm having no trouble with Master or Custom scripts, but with the Sensor scripts the ReadWrite() commands always return an array of zeros, even if I'm not in Debug mode. (I tried starting from a fresh run of Waveforms, to make sure that the debug setting was not just being excessively sticky.) Can anyone else duplicate this behavior? Or is it just me? Incidentally, the documentation for the protocol instrument and the scripts is woefully inadequate—I had to figure out how things worked by trial and error, because of the extreme lack of information in the documentation.
  8. Hi, I have a SPI slave design with 4-mode and can be auto change by custom script, after updating to 3.6.8, the POL & PHA seems be locked on the upper settings, only the POL & PHA value on the upper settings are valid, even I un-check the "Settings". How can I solve it? thanks.
  9. Hello, I am trying to avoid all of those SPI commands with higher level abstractions. The low-level example seems to help, but it is incomplete. It doesn't show how to setup or toggle the slave select lines. I presume this is done automatically, but I want manual control. I cannot find information on MicroBlaze registers. For example, let's look at XSpi_SetSlaveSelect. This is all I could find: file:///C:/Xilinx/SDK/2016.2/data/embeddedsw/XilinxProcessorIPLib/drivers/spi_v4_2/doc/html/api/group__spi__v4__1.html#ga162523a3e9b29f063701db303ac8cf17 . It's not very clear, or correct. Let me explain. I only have one slave: here is my constraint file for the SPI signals: set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { spi_0_ss_io[0] }]; #CS #IO_L5N_T0_D07_14 Sch=ja[1] set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { spi_0_io0_io }]; #MOSI #IO_L4N_T0_D05_14 Sch=ja[2] set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { spi_0_io1_io }]; #MISO #IO_L9P_T1_DQS_14 Sch=ja[3] set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { spi_0_sck_io }]; #SCK #IO_L8P_T1_D11_14 Sch=ja[4] I am using the CMOD-A7 module.These are pins on the PMOD connector. My slave select is on JA-1, as you can see. Let me demonstrate with a code snippet: while(1) { XSpi_SetSlaveSelect ( XPAR_SPI_0_BASEADDR, (u32)0x01); // This should have set my SS[0] pin to 1. It doesn't. wait a time delay XSpi_SetSlaveSelect ( XPAR_SPI_0_BASEADDR, (u32)0x00); // This should have set my SS[0] pin to 0. It's always 0, so I don't know if this worked or not. wait a time delay } This should just toggle the pin, but it doesn't. Can someone please provide a simple SPI example that is only 1 level deep (in file hierarchy)? Please include example that sets up the SPI to use the correct slave pin, and then toggles it. I included my main project file. This was originally from the Polled SPI example project, "xspi_polled_example.c", so everything else was generated by SDK. If you create a basic project with an SPI port, then you can just replace the contents of that file with that of this file and it will compile. Thank you, Richard V Temp.c
  10. Implementation SPI basys3

    Hi, I need your help please, actually I am work in an arduino communication with FPGA (Basys3), but i have a problem with the implementation, can you help me? VHDL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SPI_rx3_top is Port ( SCK : in STD_LOGIC; -- SPI input clock DATA : in STD_LOGIC; -- SPI serial data input CS : in STD_LOGIC; -- chip select input (active low) led : out STD_LOGIC_VECTOR (7 downto 0) := X"FF"); end SPI_rx3_top; architecture Behavioral of SPI_rx3_top is signal dat_reg : STD_LOGIC_VECTOR (7 downto 0); begin process (SCK) begin if (SCK'event and SCK = '1') then -- rising edge of SCK if (CS = '0') then -- SPI CS must be selected -- shift serial data into dat_reg on each rising edge -- of SCK, MSB first dat_reg <= dat_reg(6 downto 0) & DATA; end if; end if; end process; process (CS) begin if (CS'event and CS = '1') then -- update LEDs with new data on rising edge of CS led <= not dat_reg; end if; end process; end Behavioral; XDC: ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {CS}] set_property IOSTANDARD LVCMOS33 [get_ports {CS}] ##Sch name = JB2 set_property PACKAGE_PIN A16 [get_ports {DATA}] set_property IOSTANDARD LVCMOS33 [get_ports {DATA}] ##Sch name = JB3 set_property PACKAGE_PIN B15 [get_ports {SCK}] set_property IOSTANDARD LVCMOS33 [get_ports {SCK}] Warnings: [Place 30-876] Port 'SCK' is assigned to PACKAGE_PIN 'B15' which can only be used as the N side of a differential clock input. Please use the following constraint(s) to pass this DRC check: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SCK_IBUF}] [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances
  11. SPI - Arduino to Basys 3

    Arduino is the SPI Master and therefore provides the clock, SPICLK through a PMOD. How do I receive the clock in a good way on the FPGA? Vivado does not approve of checking rising_edge(SPICLK) so I though I'd put a clock buffer or something in between (not that I know why or what they do but it sounds like a good idea). At some point Vivado told me to add "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SPICLK_IBUF}]" to the constraints file, but I still got warnings and it didn't recommend I proceed. If I have the top level SPICLK connected to an IBUF_IBUFDISABLE with the disable line connected to the slave select (SS) line, I get this warning: [DRC 23-20] Rule violation (CKLD-2) Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads - Clock net spi_buf is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): IBUF_IBUFDISABLE_inst/O If I have the top level SPICLK connected to an IBUF_IBUFDISABLE and that into a BUFGCE, with the disable line connected to the slave select (SS) line and the inverse of SS into the CE, I get this warning: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. IBUF_IBUFDISABLE_inst (IBUF_IBUFDISABLE.O) is locked to IOB_X0Y25 and BUFGCE_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 Roughly the same warning was issued with just the BUFGCE. I know there are other ways of polling the input clock from the arduino and treating it as normal signal but I want to do it the "proper" way.
  12. SDK Coding

    Its been a few months since I've been introduced to FPGA design and have successfully completed some basic projects, however, while trying to effectively establish communication with devices via protocols such as uart, spi, and i2c I usually fall short. From what I understand you must enable these through the ZYNQ7 processor on block design or drop in their respective IP blocks. How to actually connect these to external devices becomes fuzzy for me and interpreting/modifying the SDK code is very difficult. In short I'm looking for some help/resources to get the ball rolling on these type of projects, and how to actually understand/develop the C code for processor myself, on both the Microzed and Zybo development boards. Thank you
  13. I've been looking over the SD library that was installed as part of the chipKIT boards (ver 1.4.1) and I get the distinct impression that it implements the SPI protocol to the SD card using bit-banging, rather than a PIC32 SPI peripheral. Is this correct? Assuming so, are there any Arduino-compatible libraries for the Wi-FIRE that utilized the SPI peripherals? Assuming not, is my best be to go with MPLAB Harmony? (I'm an old MPLAB-X guy using version 2.10 and an old peripheral library)
  14. Generate serial data

    Hi, I just bought the Analog Discovery 2 and I was looking for a way to generate serial data(uart, spi) to test my projects through the digital output pins. I was wandering since there is a logic analyser and interpreters for serial communication data. Thanks for you help
  15. CmodS6 SPI confuguration

    Hi, i am here with a few questions.I own a CmodS6, pmod Nav and pmod Bluetooth. I configurate the S6 with a microblaze mcs (the lowest brother of microblaze because of space in S6) and i want to create a SPI comunication to PmodNav but i dont know how, everything a tried doesn`t work . Also i found some libs. for nav but is still to big for fitting in S6. (Working in ISE Desing)
  16. Arty SPI Module in Slave Mode

    Hi all, I'm having trouble getting a spi module set to 'slave mode' to read data. I'm working with the Arty Board and attached is my Vivado block diagram. The SPI module that I'm having trouble with is 'axi_quad_spi_0'. I've set the IP to be in standard and unchecked Master Mode in the SPI Options. I set the FIFO to 256 and Freq Ratio 16x30. I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing. The other registers of axi_quad_spi_0 read as follows: Reg 0x60 => 0x18a Reg 0x64 => 0x25 Reg 0x70 => 0x01 whether or not the master device is sending SPI. The output from these registers seem sort of reasonable, but I would hope the flag in reg 0x64 bit 5 to go to 0 in the case axi_quad_spi_0 clks spi data in, but it isn't, which is consistent with readreg 0x6C returning 0x00. I also tried connecting outputs of a master spi module to another slave spi module 'axi_quad_spi_2' and got the same result (see block diagram). I've also tried, the xilinx spi polled mode examples and can't seem to get those working either. See below for some relevant SDK code. Can someone tell me what I might be doing wrong? Is there something more fundamental that I don't understand? Thanks! Best, Mike http://tinypic.com/view.php?pic=2vmbjg6&s=9#.WNLezbIrJaQ #define spi_dev_id2 XPAR_SPI_2_BASEADDR void simple_receive() { int data; XSpi_WriteReg(spi_dev_id2,0x60,0x1EA); XSpi_WriteReg(spi_dev_id2,0x70,0x1); XSpi_WriteReg(spi_dev_id2,0x28,0x80); data = XSpi_ReadReg(spi_dev_id2,0x6C); printf("Lithe Buffer Simple %#02x\r\n",data); }
  17. Hi, A small improvement for the SPI interpreter? We now only have a 3 wire possibility but it would be nice if we have a 4 wire too as you can see in my example where I added 1 separate channel DIO 3, the disadvantage is that I must interpret the values (like SPI MISO) of the MOSI channel by myself. Here is an example from a competitive logic analyzer; And can we have ASCII in the format too? Thanks in advance, Hans
  18. Using Zybo as SPI slave

    Hi, I want to connect the Zybo as a SPI slave to a Raspberry Pi. Vivado offers an AXI Quad SPI core but it seems to me kind of overkill for that purpose. So, my first question is what would you recommend for a simple SPI slave: using this Vivado IP Building a custom IP with any freely available SPI slave core. Let's say, I use the Vivado Quad SPI core as a slave device. Then, I am correct that I only have to connect the following ports? sck_i io0_i as MOSI io1_0 as MISO io1_t to 0 Especially, I do not need the ss signal? Third, do you know an example project how to use the Zybo (or another Zynq board) as an SPI slave. ( ideally, showing the connection to a Raspberry Pi)
  19. Hello, When using the SPI read/write Vi in the LINX Labview add on, I'm unable to select SPI_CE0 (GPIO8) on my Raspberry PI 3. I'm given an error that says that channel 8 isnt an option. Am I missing something simple, or is channel select 0 not available? SPI_CE1 (GPIO7) is an option, but the touch screen im connected to has two chips and I would like to be able to communicate with both of them. Thanks,
  20. Hi, I have a vibration sensor with an SPI interface. Can i use the Analog Discovery 2 to record the measurements to a file? if so, could you point me to some documentation that explains this? Thanks in advance! Luis
  21. Logic analyzer - SPI

    Hi, I'm trying to correctly read data from a spi line. Whenever I'm capturing data, glitches from the SS line make the software wrongly interpret the bytes. As you can see on the picture that I attached, the byte should be interpreted as 108. Here, the software cuts the byte in two and interprets it as ?96 and ?0. What should I do? I have another question. I'm trying to record two spi words of 8 bits, but that are separate by few milliseconds. How can I capture both bytes? Repeated mode makes the data acquisition great, but I am only able to capture the last word of the two (since the software clears the data whenever a new word comes in). When I am using Record mode, I always get the error: "Sample might got lost!. Reduce sample rate" which I do, but the software only successfully captures both words 1 out of 5 times. Shift and Screen mode only allows 2kHz sample rate, which is not enough. Is it possible to use the Protocol interface in the software to probe data from a spi line, like for the UART protocol interface where you click on Receive and you can see data coming in (without the need to execute a command like in the spi Protocol interface).
  22. SPI help for rookie

    Hi, I bought an analog discovery few months ago and been really happy with my purchase but for one point: I'm unable to analyze spi protocol with the logic analyzer. I have no problem using the software to see slower protocol such as uart, but when it comes to spi, I can't get the settings right to see the bits in a spi line. I'm joining a picture of the software with the data that I get... I can confirm that actual spi data is transferring in the line that I am probing and that the analog discovery cables are at the right place. Thanks for your help, Marc
  23. Interfacing DA2 with zybo Board

    Hello Everyone, Is there any good resource or tutorial to interface DAC with Zybo board, i would like to interface the DA2 pmod with zybo by making a custom ip in Vivado (VHDL) and accessing that in Xilinx SDK. If anyone have experience let me know.
  24. SPI - what about MOSI or MISO?

    Hi there, I just wanted to view the spi communication on my raspi. When setting up the "Logic" in WaveForms 2015 I added the SPI channels. But when the settings show up I can only see Select (CS), Clock (SCK) and Data which is MOSI "or" MISO!?? Can't I log them simultaneously in separate lines as it used to be?? What does the red "T" mean? Thx and Regards, nik
  25. Hello, I am exploring the Arty board. I get the a Microblaze Base system up and running and like to start programming the system, more specific - the I2C (SCL/SDA) (HIH6130 sensor) - SPI pin (TLC5947). - Build IP block written in VHDL (PWM driver). Any starting points are welcome. Regards, J.