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  1. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by follo
  2. Arduino is the SPI Master and therefore provides the clock, SPICLK through a PMOD. How do I receive the clock in a good way on the FPGA? Vivado does not approve of checking rising_edge(SPICLK) so I though I'd put a clock buffer or something in between (not that I know why or what they do but it sounds like a good idea). At some point Vivado told me to add "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SPICLK_IBUF}]" to the constraints file, but I still got warnings and it didn't recommend I proceed. If I have the top level SPICLK connected to an IBUF_IBUFDISABLE with the
  3. Hello, I am building an SPI proof of concept for the Analog Discovery 2 in LabVIEW and I am unable to get the entire thing working, despite other successful LabVIEW projects that use the Analog Discovery 2. The issue I am having is that I am capable of generating an SPI message output where the AD2 is the master, but I am unable to get the expected response in the Rx array. The pinout is the clock is on pin 2, the chip select is on pin 1, the MOSI_SISO is on pin 4 and these three outputs are connected to an oscilloscope for observation. The MISO is on pin 7 and is connected to a pu
  4. Hello everyone, I’m a newbie on working on zedboard, and I want to use my Zedboard to communicate with Pmod MIC3 this time. I did a few researches about how to use the Pmod MIC3, and I think I found something useful in another post, link: https://forum.digilentinc.com/topic/19342-driver-code-for-pmod-acl2-and-pmod-mic3/ I’m really appreciate and thanks for their help, but unfortunately I still have no idea of how to make my Pmod MIC3 to run with my Zedboard. I know Pmod MIC3 is using SPI communication protocol and I read what SPI is, link: https://reference.digilentinc.com/learn/fund
  5. New Digital Discovery user. I did not purchase this device for its excellent documentation or thorough applications examples (which are not so great), but because it can capture SPI at 800MHz with the special adapter. I understand that the Digital Discovery will stream the captured data to memory and I can save it to disk. I'm debugging a difficult SPI issue, and need to see as much detail as possible (hence the 800MHz). Out test code captures some 30,000 rows of 14 consecutive 14-bit reads at an SPI clock speed of 27.5 MHz. This is a whole lot of data. We need to see the protocol capt
  6. Hi everybody! I got a new Digilent Cmod S7 Board (Spartan 7) and after some led blinking I'm trying to program a simple High Speed SPI transmitter (just sending "01010101" for the first attempt). For this I used the Vivado Clock-Wizzard to generate both a 300MHz clock (for internal signals) and the 150MHz SPI Clock itself out of my 12 MHz onboard oscillator using the "MMCM" and basically the standard settings. Now, my problem is, when I connect my Logic Analyzer (Digilent Digital Discovery) to the 150MHz SPI Serial Clock Pin (Pin 3, which is Package Pin M3) the Duty C
  7. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  8. azn103

    Cmod S6 Quad Spi

    I recently got a Cmod S6 and was able to program it just fine. Now I want to access the Quad SPI so I can load my program directly from the SPI rather than using the Digilent Adept program. The Cmod S6 did not show any references to how to program that part. How do you program the PROM?
  9. Hi With the waveforms tool is it possible using python scripting in the Waveforms platform to do the following ?? Use the Digilent Analogue discovery 2 - Attach a device like a PMOD device eg accelerometer https://store.digilentinc.com/pmod-acl-3-axis-accelerometer/ using the Analogue discovery 2 ability to chat SPI & IC2 - pmod DEVICES SUPPORT 12-pin Pmod connector with SPI interface and 2×4-pin I²C interface - Then using the read information from the PMOD device treat it like an extra oscilloscope channel . Either as a Analog channel
  10. Hi there, I am in need of help communicating with my Pmod AD5 using the SPI on raspberry pi 3. I am pretty new to SPI and have troubleshooted and searched the web for solutions over the past week but have yet to solve this problem. Here are some of the steps that I have done: 1) managed to read values using the Arduino Library linked on the product page and with an Arduino UNO, by connecting VCC of Pmod AD5 to 5V (I am not sure what I cannot read anything when connected to 3.3V) 2) understood what SPI is about and what the Arduino Library is doing (or what I think was logical) - rea
  11. I am trying to use a DAQ to analyze I2C, SPI, and UART signals and then classify them, so they have to be the actual output signals from the Cora Z7 board. However, I am limited due to the project itself to use only the General Purpose I/O pins (IO0-IOA(IO42)). Is it possible to funnel the SPI, I2C, and UARt signals through these pins, or can you only use the specified pins, such as SDA/SCL, MISO/MOSI, or the USB UART bridge to do this?
  12. I am starting with working design for the CMOD S7 where I program the device through SDK and all functionality works as intended. Now where I am falling short is getting the program to run out of the SPI Flash. I have been following the "How To Store Your SDK Project in SPI Flash" guide from Digilent in order to put a Microblaze design into SPI Flash on the CMOD S7 located at the link here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start There is a recommended offset of 0x00300000 for the CMOD A7 - My question is what is the recommended o
  13. Hello, I've been strugling with de micro-sd card in Nexys-4 for quite some time. I'm using the code at sd_spi.vhd by Lawrence Wilkinson, but the FPGA never gets a valid answer from the card so it keeps looping forever (CMD8) I think I've checked all the obvious things : - Trying an old card, just in case SDHC was not properly suported - Booting the FPGA from the SD card (not USB), to check that the physical circuits were working properly - Trying with 3 different Nexys 4 boards - Lowering clock frequency to only a few hertzs (normal speed should be 50MHz, and a c
  14. Hello I have a microblaze running a LwIP server adapted from the lwIP server example where everything works fine. LwIP stops working when I use another peripheral with an interrupt attached to it. In my case I have an SPI EEprom running perfectly, but after initialization LwIP stops working. The EEprom code is also standard code from the example. Interrupts are all connected to the microblaze with a concat IP. Has anybody experience in this topic?
  15. i wanted to interface multiple digital serialiser with arty A7 35T board through pmod pins. And transmit the same data through UART. help me with the verilog code and other resource.
  16. Victor McKeighan

    Victor

    I'm using Xilinx ISE suite to design, test and program the Cmod S6 board. At this point I am able to configure the Spartan6 FPGA with a bit file over the USB connection (although I have not verified functionality), but I'm having a problem programming the serial PROM. Here is the report I get from the iMPACT tool: INFO:iMPACT - Current time: 5 Jul 2018 14:00:55 // *** BATCH CMD : Program -p 1 -dataWidth 1 -spionly -e -v -loadfpga PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 25000000. Validating chain... Boundary-scan chain v
  17. Hello, We are trying to generate the SPI protocols signals from the Zybo-Z710 board, which uses Zynq-7000 SoC. Since, the PS section of the chip contains two SPI modules. Can anyone tells me the procedure for activating the SPI line inside the PS. I want to use this SPI lines to transfer data and provide control to the another module. Thanks AMOL
  18. Hi, A small improvement for the SPI interpreter? We now only have a 3 wire possibility but it would be nice if we have a 4 wire too as you can see in my example where I added 1 separate channel DIO 3, the disadvantage is that I must interpret the values (like SPI MISO) of the MOSI channel by myself. Here is an example from a competitive logic analyzer; And can we have ASCII in the format too? Thanks in advance, Hans
  19. Hi everyone, After having succesfully managed to use de XADC of the Zybo Z7010 board as explained in this post, I am now trying to use a DAC Pmod (reference and documentation here). After having checked the documentation, I have tried to write the SPI connection to the DAC (please find the verilog file and simulation in the attached files). Note, that I have decided to set the l_dac signal to 0 to enable continuous output to an oscilloscope. The simulation seems to run well to me and to be in accordance with the documentation, however, the result is not satisfactory. I
  20. Analog Discovery is a nice tool to use to emulate MASTER SPI and debug. I have some students who are trying to use it to emulate a SPI Master Device to interface to a peripheral resolver chip from Analog Devices before they implement the design in an FPGA. The Analog Devices chip has !WR/!FRAME sync signal in addition to the the main SPI. Is there any easy way for them to use the SPI protocal MASTER mode (using the setup on the SPI MASTER tab) at the same time with generating a pattern signal for !WR/!FRAME that is in sync with SCLK? If so, how could they reference the frame signal to
  21. Hi all, I'm having trouble getting a spi module set to 'slave mode' to read data. I'm working with the Arty Board and attached is my Vivado block diagram. The SPI module that I'm having trouble with is 'axi_quad_spi_0'. I've set the IP to be in standard and unchecked Master Mode in the SPI Options. I set the FIFO to 256 and Freq Ratio 16x30. I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing. The other registers of axi_quad_spi_0 read as foll
  22. I need to spy on an SPI connection for a long period of time which will require timestamps on the data to find approximate times of transmission. As this is not possible in Waveforms (which is a real shame) has anyone written any software that uses the SDK to do something similar to this? It would save me a bit a work if there was already an existing solution. - Callum
  23. I'm using the Analog Discovery 2 and on WaveForms 3.8.2 I cannot figure out how to send and receive SPI data. I can read SPI traffic fine through the Logic Analyzer, but I've had no luck with the Protocol analyzer. I have some hardware that I'm debugging that sends commands to a SPI device. The Logic Analyzer tool shows this just fine (below). What I'd like to do is send other SPI commands using the Protocol tab but I've had no luck figuring out how to send commands (properly). As a first step, I'd like to reproduce what I see below in the logic analyzer but do it instead in the protocol
  24. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Th
  25. I have been following this tutorial and have had no luck. I am uncertain about how to configure the QSPI IP, because the tutorial starts assuming that I have done that part successfully, so I am not even sure if this is the root of my problem. I have tried these two configurations of this IP, compiled them, and exported them to the SDK, and none of them solved the problem: I made sure JP4 is in the QSPI position. On step 3.1 in the tutorial, I can see that the FPGA is programmed successfully and I see the following output (since I chose not comment out the VERBOSE define as su