Search the Community

Showing results for tags 'spartan6'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 10 results

  1. hi.. ! I need a fpga devolpment board with VGA and HDMI as input and HDMI or DVI or both as output. i googled but not find a single board with these connectors together. Thanks in Advance.
  2. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F
  3. Hi, I recently purchased the pmodbt2 bluetooth interface module and tried interfacing it with the Atlys board. I used the GPIO demo bit file which was given in the forum for verification (after modifying it), but I was not able to see the output in the terminal software (Teraterm). I followed the instructions given in the demo, but I was not able to see the output; are there any specific changes I need to make in the module or in the terminal software? Can someone help me out with this? Ishan
  4. Hassan Iqbal

    Aligning two video sources in Atlys Spartan 6

    Hi, For a project, I want to align two input HDMI video sources in Atlys Spartan 6. I want to implement an asynchronous FIFO which will synchronize video source B with video source A timings (picture attached). However, the FIFO should be of the size to store atleast 8 MB (frame size of each video source = 1920*1080*32 bits). How to implement this asynchronous FIFO in Atlys Spartan 6? My atlys kit has MIRA P3R1GE4JGF DDR2 IC on it instead of Micron MT47H64M16xx-25E which is in older boards of Atlys Spartan 6. I am using ISE Design Suite 14.2 and running Xapp495. The frame rate that I am working on is 120 FPS and resolution is 1080p. The pixel speed is 146.3616Mhz. If possible, then share some sample code which can be modified to implement this FIFO. Thanking you in anticipation.
  5. Hi: I would like to implement an application in my fpga to communicate to the PC. I don't want to use the SDK, I prefer VHDL. So, I can generate a Xilinx LogiCORE Tri-Mode Ethernet MAC using Xilinx's Coregen, but I don't know how to connect it. For example, the global clock is 125Mhz, and the atlys only provides me a 100Mhz. Should I use a clock generator? Thanks.
  6. yashkarundi

    adc 1 channel 100khz interface with spartan6

    Hello, As I figured out from the datasheet of the board, Spartan6 Atlys board has no ADC intefaced to it. We can do so by making a custom PCB using one of the ADC chips available in the market. COuld someone help me out with the design steps and an overview as to how I should design the ADC board. Also, how should i connect the board to the spartan 6 board
  7. hi i am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip. my frame is:- constant udp_frameA :frame60:= (x"FF",x"FF",x"FF",x"FF", -- mac dest x"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- mac src x"08",x"00",x"45",x"00", -- IP header x"00",x"2E",x"00",x"00", x"00",x"00",x"40",x"11", x"7A",x"C0",x"00",x"00", -- IP src x"00",x"00",x"FF",x"FF", -- IP dest x"FF",x"FF",x"00",x"00", -- port src x"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A" x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41"); and i am getting same frame on simulation and chipScope but i am not getting this frame in proper order on Wireshark. Wireshark result attached with it. please find this attachment. please respond me as soon as possible.
  8. Hmidi

    matrix multiplication using microblaze

    I want to do a matrix multiplication using an Atlys Spartan-6 xc6slx45,I connect 4 microblazes and I want to add a Noc,but I need a design tool for a Noc.I didn't find any one which is compatible with windows because I use xilinx ISE 14.7.can any one has an idea about that??

    Product 400 Mhz Clock In Atlys Board

    hi my working is on atlys board (spartan 6)i want to create a clock with 400 MHz frequency , when i use the ip-core(clocking - clocking Wizard 3.6) the error will be displayed . How i can write this code manualy ? the error is: thanks

    Fpga 1

    Dear Sir/Madam My name is Revanasidha K Jambgi i am doing a project is to implement image processing algorithms such as (Sobel edge detection and color reduction for single image data) on FPGA I have NEXYS3 board which has spartan 6. I request you to help me regarding this. I have to load the image file into the FPGA board and should have an access toeach pixel of the image. Please send me the snap shots of the process. ORwrite me where i can get this stuff. I searched in web for days together but couldn’t find it.