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Found 5 results

  1. Hello everyone! I got my hands on a Diligent Nexys 2 Spartan 3E Board in this pandemic from a prof next doors. I am proficient in Verilog HDL and VHDL. I want to test my codes on this board, but in the board select menu, there is no option to select for this board. After Googling this stuff, I found that the production of this board has stopped. Is there any way in which I can program this board using Xilinx Vivado ISE / (or any other software)?
  2. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  3. tomii

    Howdy

    Hey everybody! Taught myself just enough Verilog to be dangerous from 2013-2015 or so. Wrote a bunch of (boring) articles for a now-defunct trade site (absorbed into EETimes) about the process. Some of that stuff might still be available if you're lucky enough to find it. Did most of my learning on Opal Kelly XEM3005 - which I gotta say is an *excellent* platform (get yourself a breakout board, tho). I've started doing some stuff with Digilent devices a couple years ago, but haven't had any real opportunity to dig in to the "new" Arty or Zynq-based boards. So sitting around my home "lab," I've got a few Opal Kelly boards (XEM3001, XEM3005, and a couple others) - I love the FrontPanel system they've developed. I've also got an Arty (35T) and now a Cora (low-end Zedboard), and I'm itching to learn some stuff there. I also do a fair amount of bare-metal embedded when I need to (e.g. Atmel/Microchip microcontrollers), and have also recently been doing some stuff with embedded Linux on the pi platform. Lastly, let's talk about the registration process. Jimminy Christmas, it took me and another engineer 8 tries to get validated! Holy cow, am I st00pid, or what? -Tom
  4. Carson

    Xilinx FPGA Spartan 6

    Hi, I'm currently developing an embedded system using an FPGA board, which has an embedded Digilent USB JTAG programmer that enables the FPGA to be configured via the USB port on the PCIe bus. I’m trying to figure out how to use the Digilent linux configuration program “djtgcfg” to program a .bit file into the FPGA but noticed that it is not able to properly identify the Xilinx Spartan 6 chip (pn XC6SLX45T) on the board. I think the program is not able to find the Spartan device on a file “jtscdvclist.txt”, which is a lookup file containing a lot of Xilinx parts. However, I am not able to see the XC6SLX45T on the list. The closest that I could find was the XC6SLX (without the T on the end) on that list. BTW, I also see this problem when I use the Xilinx ISE impact tool plugin. Does Digilent support this particular Xilinx chip? [[email protected]_Server_devpc104 bin64]$ ./djtgcfg init -d RTD16850149 Initializing scan chain... Found Device ID: 44028093 Found Device ID: d5058093 Found 2 device(s): Device 0: XCF16P Device 1: XC6SLX ? XILINX{ FAMILY{ ;--- FPGAs XC2S$ 00600000h 0FE00000h XC2S$E 00A00000h 0FE00000h XC3S$ 01400000h 0FE00000h XC3SD$A 06800000h 0FE00000h XC3S$AN 02600000h 0FE00000h XC3S$A 02200000h 0FE00000h XC3S$E 01C00000h 0FE00000h XC6SLX$ 04000000h 0FE00000h XC7A$T 03620000h 0FFF0000h XC7A$T 03630000h 0FFF0000h XC7K$T 03640000h 0FEE0000h XC7VX$T 03660000h 0FFF0000h XC7VX$T 03680000h 0FFE0000h XC7Z$ 03700000h 0FF00000h XCV$ 00600000h 0FE00000h XCV$E 00A00000h 0FE00000h XC2V$ 01000000h 0FE00000h XC2VP$ 01200000h 0FE00000h XC4VFX$ 01E00000h 0FE00000h XC4VLX$ 01600000h 0FE00000h XC4VSX$ 02000000h 0FE00000h XC5VFX$T 03200000h 0FE00000h XC5VLX$ 02800000h 0FE00000h XC5VLX$T 02a00000h 0FE00000h XC5VSX$T 02e00000h 0FE00000h XC5VTX$T 04500000h 0FE00000h XC6VCX$T 042c0000h 0FFE0000h XC6VLX$T 04240000h 0FFE0000h XC6VLX760T 04230000h 0FFF0000h XC6VSX$T 04280000h 0FFE0000h XC6SLX${ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 4 04000093h 0FFFFFFFh 16 04002093h 0FFFFFFFh 25 04004093h 0FFFFFFFh 45 04008093h 0FFFFFFFh 150 0401D093h 0FFFFFFFh } } Thanks, Carson
  5. Hello Everyone, I need help determining whether the JTAG-HS2 is compatible with Xilinx Spartan XC3S400 FPGA JTAG. I'm brand new to Xilinx FPGA Thanks, Vu