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Found 8 results

  1. Hello everyone I am selling my almost brand-new Xilinx Nexys 3 Trainer Board w/ Spartan 6 FPGA. I've only used it for about 1 week and it is in absolute Mint condition. I am choosing to sell it because my new job at a startup uses Altera's line of products so I will be getting an Altera FPGA Unfortunately I just got my Nexys 3 so I am try to get whatever money I can for it. A link to this product on the Digilent site can be found below: https://store.digilentinc.com/nexys-3-spartan-6-fpga-trainer-board-limited-time-see-nexys4-ddr/ As you can see, it's worth $270 on the website, the total comes to over $300 if you order it from the store. I was hoping I could get around $200 if possible but am definitely open to haggling depending on the demand. Please let me know if you are interested! This is a great board to build projects and can do a ton of things! Inbox me or comment here
  2. Hi, We're designing several boards that have a mixture of XIlinx Fpgas. One such board has multiple Virtex 5's, a Kintex 7 and a Spartan 6. We want to use a JTAG-SMT2 board to both configure the Fpgas and then use Chipscope for debugging. This means that all the Fpgas would be on a single JTAG chain. Has this been done before? Should a configuration like this work? We would be driving (via USB) the JTAG-SMT2 from an embedded linux processor and use the ADEPT SDK for configuration as well as implementing USB over Ethernet so that the Xilinx debug tools could run seamlessly on a laptop. Thanks Marc Howard
  3. Hi, I am trying to program Spartan 6 FPGA(6SLX25FTG256) with Jtag HS2 in Ubuntu 14.04. I can see the device with command "sudo djtgcfg enum": Found 1 device(s) Device: JtagHs2 Product Name: Digilent JTAG-HS2 User Name: JtagHs2 Serial Number: 210249A143CA I can also detect the FPGA using command "sudo djtgcfg init -d JtagHs2": Initializing scan chain... Found Device ID: 24004093 Found 1 device(s): Device 0: XC6SLX ? But when I tried to program the FPGA, it always failed. I tried with .bit file first using the following command: sudo djtgcfg prog -d JtagHs2 -i 0 -f fpga_firmware.bit Then it gave the following error: "ERROR: failed to set programming file" I then suspected it might be permission issue of the fpga firmware. I then changed the permission for both .bit and .bin files: sudo chmod 777 fpga_firmware.bit sudo chmod 777 fpga_firmware.bin and then tried to program again. But it gave the same error--- "ERROR: failed to set programming file". I then tried to program with .bin file: sudo djtgcfg prog -d JtagHs2 -i 0 -f fpga_firmware.bin This time it seems it recognizes the file and start to program, but it fails and gives error like this: "Programming device. Do not touch your board. This may take a few minutes... ERROR: failed to program device with file fpga_firmware.bin" It seems that the Digilent Adept software I installed does not support Xilinx Spartan 6. Could anyone tell me what is wrong? Why it can not program Spartan 6? Thank you.
  4. melpin@digilent

    Audio Processor

    I am building an audio processor with effects in my final year project using Spartan 6 and there is a problem i am facing. Since my project guide has left my institute , I am facing a few difficulties of which this is one of them. The following is the code for audio playback . When i use it without the clock divider (On board clock of 4 MHz) process i am able to hear the audio . When i change the ADC Clock (Clock Divider from 4 MHz to 44.1 KHz ) i am unable to hear anything . Why is it so. The test bench shows that the ADC clock is divided to 44.1 KHz but its not giving an on board output. ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:19:31 01/03/2016 -- Design Name: -- Module Name: ADC_DAC_interface - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity ADC_DAC_interface is Port ( ------- FPGA global inputs -------- F_RESET : in STD_LOGIC; F_CLK_4MHz : in STD_LOGIC; --------------- ADC interface (AD7938) ------------ F_IL : IN STD_LOGIC_VECTOR (1 downto 0); -- Switches for ADC i/p channel selection F_ADC_D : inout STD_LOGIC_VECTOR (11 downto 0); F_ADC_CLK : out STD_LOGIC; -- ADC clock F_ADC_CS_BAR : out std_logic; --chip select F_ADC_CONVST_BAR: out std_logic; --conversion start F_ADC_WR_BAR : out std_logic; --write F_ADC_RD_BAR : out std_logic; --read --------------- DAC interface (TLV5619) ------------ F_DAC_D : out STD_LOGIC_VECTOR (11 downto 0); F_WE_BAR : out STD_LOGIC;--13/2 F_CS1_BAR : out STD_LOGIC; F_CS2_BAR : out STD_LOGIC; F_CS3_BAR : out STD_LOGIC; F_CS4_BAR : out STD_LOGIC -- chipscope_clk : out STD_LOGIC ); end ADC_DAC_interface; architecture Behavioral of ADC_DAC_interface is type state is (reset_s, write_cr, write_cr2, start_conv, check_count_done, read_data); signal prsnt_s, next_s : state; signal control_word : std_logic_vector(11 downto 0); -- signals to count upto 16 instead of using BUSY pin -- signal count_16 : std_logic_vector(3 downto 0):= "0000"; signal start_count : std_logic:= '0'; signal count_done: std_logic:= '0'; signal reset_counter : std_logic:= '1'; signal Clk_in : std_logic; signal Clk_mod : std_logic; signal divide_value : integer; signal counter,divide : integer := 90; signal data_out_s: std_logic; signal CLK : STD_LOGIC; begin CLK <= F_CLK_4MHz; Clk_in <= CLK; divide_value <= divide; process(Clk_in) begin if( rising_edge(Clk_in) ) then if(counter < divide/2-1) then counter <= counter + 1; Clk_mod <= '0'; elsif(counter < divide-1) then counter <= counter + 1; Clk_mod <= '1'; else Clk_mod <= '0'; counter <= 0; end if; end if; end process; F_ADC_CLK <= Clk_mod; -- BUFG_inst : BUFG -- port map ( -- O => clk, -- Clock buffer output -- I => F_CLK_4MHz -- Clock buffer input -- ); --address_s <= channel_switch(1 downto 0); control_word <= "00010" & F_IL(1) & F_IL(0) & "00001"; -- Count 16 clock cycles (time taken for ADC to convert the sampled input) process(reset_counter, clk, start_count,f_reset) begin if(F_RESET = '1' or reset_counter = '1') then count_16 <= "0000"; elsif (start_count = '1') then if(clk'event and clk = '1') then count_16 <= count_16 + '1'; end if; end if; end process; count_done <= count_16(0) and count_16(1) and count_16(2) and count_16(3); -------------------------- State Transition ------------------------- process(F_RESET, clk) begin if(F_RESET = '1') then prsnt_s <= reset_s; elsif(clk'event and clk = '1') then prsnt_s <= next_s; end if; end process; ------------------ Conditions for State change --------------------- process(F_RESET, prsnt_s, count_done) begin case prsnt_s is when reset_s => if F_RESET = '1' then next_s <= reset_s; -- When reset becomes 0, else -- change state to write_cr next_s <= write_cr; end if; when write_cr => next_s <= write_cr2; when write_cr2 => next_s <= start_conv; when start_conv => next_s <= check_count_done; when check_count_done => if count_done = '0' then next_s <= check_count_done; -- ADC AD7938 takes 13 cycles to convert a else -- sampled data. So a 4-bit counter is used here. next_s <= read_data; -- (Previously, BUSY pin was checked. When busy = 0, end if; -- change state to read_data) when read_data => next_s <= write_cr; when others => next_s <= reset_s; end case; end process; --------------------- Outputs at each state --------------------------------- process(prsnt_s, control_word,clk) begin case prsnt_s is when reset_s => F_ADC_CS_BAR <= '1'; F_ADC_CONVST_BAR <= '1'; F_ADC_WR_BAR <= '1'; -- RESET State F_ADC_RD_BAR <= '1'; data_out_s <= '0'; F_CS1_BAR <= '1'; F_CS2_BAR <= '1'; F_CS3_BAR <= '1'; F_CS4_BAR <= '1'; F_WE_BAR <= '0'; start_count <= '0'; reset_counter <= '1'; when write_cr => F_ADC_CS_BAR <= '0'; F_ADC_CONVST_BAR <= '1'; F_ADC_WR_BAR <= '0'; -- Write Control Word F_ADC_RD_BAR <= '1'; -- into Control register of ADC 7938 data_out_s <= '1'; F_CS1_BAR <= '1'; F_CS2_BAR <= '1'; F_CS3_BAR <= '1'; F_CS4_BAR <= '1'; F_WE_BAR <= '0'; start_count <= '0'; reset_counter <= '1'; when write_cr2 => F_ADC_CS_BAR <= '0'; F_ADC_CONVST_BAR <= '1'; F_ADC_WR_BAR <= '1'; -- Control Word is latched into ADC 7938 F_ADC_RD_BAR <= '1'; -- at the rising edge of WR-bar signal data_out_s <= '1'; F_CS1_BAR <= '1'; F_CS2_BAR <= '1'; F_CS3_BAR <= '1'; F_CS4_BAR <= '1'; F_WE_BAR <= '0'; start_count <= '0'; reset_counter <= '1'; when start_conv => F_ADC_CS_BAR <= '1'; F_ADC_CONVST_BAR <= '0'; -- Conversion is started. F_ADC_WR_BAR <= '1'; -- ADC drives BUSY output pin HIGH F_ADC_RD_BAR <= '1'; data_out_s <= '0'; F_CS1_BAR <= '1'; F_CS2_BAR <= '1'; F_CS3_BAR <= '1'; F_CS4_BAR <= '1'; F_WE_BAR <= '0'; start_count <= '1'; reset_counter <= '0'; when check_count_done => F_ADC_CS_BAR <= '1'; F_ADC_CONVST_BAR <= '0'; -- CONVST_BAR pin is driven LOW until F_ADC_WR_BAR <= '1'; -- ADC-BUSY pin goes LOW F_ADC_RD_BAR <= '1'; data_out_s <= '0'; F_CS1_BAR <= '1'; F_CS2_BAR <= '1'; F_CS3_BAR <= '1'; F_CS4_BAR <= '1'; F_WE_BAR <= '0'; start_count <= '1'; reset_counter <= '0'; when read_data => F_ADC_CS_BAR <= '0'; -- Once ADC-BUSY goes LOW, data is F_ADC_CONVST_BAR <= '1'; -- read from ADC and applied to DAC F_ADC_WR_BAR <= '1'; F_ADC_RD_BAR <= '0'; data_out_s <= '0'; F_CS1_BAR <= '0'; F_CS2_BAR <= '0'; F_CS3_BAR <= '0'; F_CS4_BAR <= '0'; F_WE_BAR <= NOT clk; start_count <= '0'; reset_counter <= '1'; end case; end process; ------ Controlling bidirectional operation of databus -------- F_ADC_D(11 downto 0) <= control_word when data_out_s = '1' else (others => 'Z'); F_DAC_D <= F_ADC_D; --process(F_RESET, clk) --begin -- if(F_RESET = '1') then -- F_DAC_D <= (others=>'0'); -- elsif(clk'event and clk = '1') then -- F_DAC_D <= F_ADC_D; -- end if; --end process; end Behavioral;
  5. I'm a college professor trying to select a toolchain for an upcoming class based on the Cmod F6 board (a Xilinx Spartan 6). I am new to FPGAs; moving over from an analog background to cover for a colleague who is retiring, so all this is quite new to me. Xilinx seems to want new users to use their Vivado toolset rather than ISE Webpack. In fact, it appears the Vivado is the only choice to run on our lab computers that now run Windows 10. Vivado supports the Spartan 6 on the Cmod F6, so that part seems to work. My questions: 1) What is the purpose of Digilent Adept - just to load the binaries or is it a replacement front-end for the Vivado synthesis tool? Or is it simplest to work entirely within Vivado? (if not, will Adept work on Win 10?) 2) How does one get the FPGA code to run when power is applied, ie to run from the non-volatile storage? It seems programming the SPI flash requires Xilix's iMPACT software, which is only available for their deprecated ISE Wepack, not Vivado. Or does one install just the iMPACT tool from Webpack on top of the Vivado installation? I'm sure these are common questions - how to get Digilent's FPGA Cmod board programmed using the current Windows OS; my apologies for being too new to this to figure it out. Thanks for any guidance that will help my students!
  6. Argoth

    Nexys 3 With Pmodrf2

    Hello, I would like to you use PmodRF2 with Nexys 3 board in my project at school. So I am looking for some reference design in VHDL for Spartan 6. Do you have something like that? http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3&CFID=7442452&CFTOKEN=e41455559876637a-43DBCAA9-5056-0201-028B3A77A60DF63D https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,927&Prod=PMOD-RF2 Best regards Marty
  7. sarathtv2

    Selecting An Fpga Board

    Hi all, I am new to fpga so need some help in selecting a board. I need a spartan 6 board which has an flash memory and can be programmed using a JTAG. not through usb jtag. can some one help me by listing all such boards ? Thanks in advance sarath
  8. Alex

    Vmod CAM Atlys demo port to Genesys

    If I want to port the current Vmod CAM Atlys Demo to Genesys. Do I only need to change the UCF and target device?