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Showing results for tags 'slew rate'.
Hello. Reading the Manual I saw the following. 5. Digital I/O Figure 22 shows half of the Digital I/O pin circuitry (the other half is symmetrical). J3 is the Analog Discovery 2 user signal connector.General purpose FPGA I/O pins are used for Analog Discovery 2 Digital I/O. FPGA pins are set to SLOW slew rate and 4mA drive strength, with no internal pull. PTC thermistors provide thermal protection in case of shortcuts. Schottky Diodes double the internal FPGA ESD protection diodes for increasing the acceptable current in case of overvoltage. Nominal resistance of the PTCs (220Ω
Hello all, Chapter 2 of digital discovery (DD) manual mentioned about the possibility of output strength and slew adjustment. In waveform 2015 (e.g. 3.6.8), driver strength and slew can be adjusted in "supplies" manual. However, I couldn't find any API definition for this item. May I know where to find such API? Many thanks. HPLam P.s. Here is the quote from Ch.2 of DD's manual "The output strength can be set from 2mA to 16mA. The output slew rate can be set as: Quiet, Slow or Fast."