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  1. Hi all, I'm having trouble getting a spi module set to 'slave mode' to read data. I'm working with the Arty Board and attached is my Vivado block diagram. The SPI module that I'm having trouble with is 'axi_quad_spi_0'. I've set the IP to be in standard and unchecked Master Mode in the SPI Options. I set the FIFO to 256 and Freq Ratio 16x30. I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing. The other registers of axi_quad_spi_0 read as follows: Reg 0x60 => 0x18a Reg 0x64 => 0x25 Reg 0x70 => 0x01 whether or not the master device is sending SPI. The output from these registers seem sort of reasonable, but I would hope the flag in reg 0x64 bit 5 to go to 0 in the case axi_quad_spi_0 clks spi data in, but it isn't, which is consistent with readreg 0x6C returning 0x00. I also tried connecting outputs of a master spi module to another slave spi module 'axi_quad_spi_2' and got the same result (see block diagram). I've also tried, the xilinx spi polled mode examples and can't seem to get those working either. See below for some relevant SDK code. Can someone tell me what I might be doing wrong? Is there something more fundamental that I don't understand? Thanks! Best, Mike http://tinypic.com/view.php?pic=2vmbjg6&s=9#.WNLezbIrJaQ #define spi_dev_id2 XPAR_SPI_2_BASEADDR void simple_receive() { int data; XSpi_WriteReg(spi_dev_id2,0x60,0x1EA); XSpi_WriteReg(spi_dev_id2,0x70,0x1); XSpi_WriteReg(spi_dev_id2,0x28,0x80); data = XSpi_ReadReg(spi_dev_id2,0x6C); printf("Lithe Buffer Simple %#02x\r\n",data); }