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  1. I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller_0). Up to now, I'am reading trash data from the IP output, so I suppose I've made a mistake in the connections or in the data acquisition or something else. I've not seen any example of a verilog instantiation of the IP, so please let me know if there's any out there. For making the connections, I've followed the schematic in the reference manual. I'm posting my top level design and I'm also attaching the constraint