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Hello, I'm trying to use the AD2 pattern generator to create a (digital) sine wave using a value table table. I connected the external trigger to a clock of 10MHz, to create a sine with the frequency of 10/1024 MHz (with 1024 being the size of the table). When I compare the resulting sine wave to a sine wave generated by an FPGA, using a look-up table with the same size and clock, I see that both signals drift apart from each other, even though both of them seem to have the same period. Am I using this tool the wrong way? Is my setting for a trigger wrong somehow?

i want to generate sine wave on dac (pmodda3)(http://www.analog.com/media/en/technical-documentation/data-sheets/AD5541A.pdf)and i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;