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Found 6 results

  1. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store
  2. Hello, dear FPGA enthusiasts! Currently, I have been working with my OV7670 camera and can present it on an HDMI screen. However, this was done without a simulation. What I want to do right now is to use a TPG provided from Xlinix in my design and remove the OV7670 fully. However, the problem is that I really don't know how to go next since I am using uB together with a VDMA and TPG. I know that you can include the ELF file from the uB in order to simulate your design together with uB. My question to you is where I can find C code for the TPG used in the ne
  3. hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values md5.txt1.txt pancham_round.txt
  4. Hi! I'm currently implementing a game with led matrix using basys3. But sometimes it become hard to understand the mistake in the code if there is a problem with the code. I know how to use testbenches but in my case it's not really helpful. So I want to make a simulation with real time physical inputs. I mean the simulation show the results when I press a push button. Is it possible?
  5. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the sam
  6. Hi I have done an intro to vivado simulation in Verilog based on the assignment I have done in ISE http://m.instructables.com/id/How-to-Use-Vivado-Simluation/?ALLSTEPS