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Showing results for tags 'signals'.
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Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs and outputs and see how the timing diagram behaves and try to implement the logic based off of that? Or should I be first be treating this as a "state machine" and draw a systematic schematic of showing all the inputs and outputs, showing when they should go HIGH or LOW at their certain times? Are timing diagrams usually implemented in a state machine logical flow? Was hoping to gain some knowledge and understanding from the people who are experienced writing Verilog logic based off of timing diagrams and was hoping to see your systematic approach of how it should be implemented as if I was an engineer. Thank You.
Hello, For a project in one of my courses my adviser asked me to find a way to control the sample rate and record length in the Analog Discovery in order to understand how to use the FFT module. Thank you, cjobi247