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Showing results for tags 'signal integrity'.
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I'm doing initial bring-up and testing of a PMOD module for PRBS testing and eye measurements on moderately fast (500 Mbps range) single-ended signals. It contains an 8 GHz bandwidth sampling oscilloscope which uses a clever equivalent-time version of successive approximation to digitize a repeating signal with <100 ps resolution, for less than $50 in parts plus an FPGA board. My current test setup plugs the PMOD into high-speed PMOD port C on a Zybo. From my understanding this is routed as 100 ohm differential pairs, but the single-ended impedance isn't specified anywhere in the documentation that I can find. All of the transmission lines on my PMOD are impedance matched to 50 ohms, as are the connectors (edge launch SMA good to 20 GHz) and the cable (Crystek Microwave semi-rigid coax). Here's a pic of my board. When I loop the transmit and receive SMA connectors together with a 50 ohm coax patch cable, I get the following eye as measured by the PMOD oscilloscope. Timebase is 100ps per sample, 1 ns per major scale division. Although the eye opening is pretty decent, there's a big step that I think is probably due to a reflection in the line. Can any Digilent engineers enlighten me here? Preliminary calculations suggest that this eye closing is consistent with a ~75 ohm Zo stub about ~40mm long driving a 50 ohm line. What is the overall trace length on the Zybo from FPGA package to the header for pin 1 of PMOD C? What is the single-ended impedance of this line? Pin 2, the differential mate, is grounded. (This is mostly to satisfy my curiosity, I know that the pin header isn't exactly controlled impedance. Down the road I plan to add an active repeater on the PMOD to clean up the TX eye.)
Greetings, I need to know what is the output characteristic impedance of the VHDC connectors on the Genesys Virtex 5 FPGA Develpment Board. The datasheet only says they are impedance-controlled matched pairs and the schematic does not have this info. Some online forums said SCSI is defined by ANSI X3.13, the nominal diff cable impedance is 122 Ohms and I want to check if my board IO is consistent with this standard or not. I need to design a mating board to convert high speed differential signals into single ended, and signal integrity is a big deal. Thanks in advance, Emanuel
Hello, I am prototyping a concept on the Nexys Video Board. I would like to use the FMC connector and build my own FMC-like board. I will be using both GTP and SERDES outputs. considering the speeds (2.4Gbps, 300Mbps) I need to make sure signal integrity is up to standards all the way from FPGA Ball to the chip on my FMC board including connectors and co. Therefore I need info on the Nexys Video Layout. could you provide: -full layout so I can do post-layout model extraction for the GTP and SERDES io lines, for simulation with Hyperlynx? or -hyperlynx models of the lines? best regards. toby