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Showing results for tags 'signal integrity'.
I'm doing initial bring-up and testing of a PMOD module for PRBS testing and eye measurements on moderately fast (500 Mbps range) single-ended signals. It contains an 8 GHz bandwidth sampling oscilloscope which uses a clever equivalent-time version of successive approximation to digitize a repeating signal with <100 ps resolution, for less than $50 in parts plus an FPGA board. My current test setup plugs the PMOD into high-speed PMOD port C on a Zybo. From my understanding this is routed as 100 ohm differential pairs, but the single-ended impedance isn't specified anywhere in the docum
Greetings, I need to know what is the output characteristic impedance of the VHDC connectors on the Genesys Virtex 5 FPGA Develpment Board. The datasheet only says they are impedance-controlled matched pairs and the schematic does not have this info. Some online forums said SCSI is defined by ANSI X3.13, the nominal diff cable impedance is 122 Ohms and I want to check if my board IO is consistent with this standard or not. I need to design a mating board to convert high speed differential signals into single ended, and signal integrity is a big deal. Thanks in advance,
Hello, I am prototyping a concept on the Nexys Video Board. I would like to use the FMC connector and build my own FMC-like board. I will be using both GTP and SERDES outputs. considering the speeds (2.4Gbps, 300Mbps) I need to make sure signal integrity is up to standards all the way from FPGA Ball to the chip on my FMC board including connectors and co. Therefore I need info on the Nexys Video Layout. could you provide: -full layout so I can do post-layout model extraction for the GTP and SERDES io lines, for simulation with Hyperlynx? or -hyperlyn