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Found 52 results

  1. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  2. """ DWF Python Example Author: Digilent, Inc. Revision: 2015/02/05 Requires: Python 2.7 Start synchronized the AWG outputs of multiple Analog Discovery devices. Connect the Trigger-1 pin of each device together. """ from ctypes import * import time import sys if sys.platform.startswith("win"): dwf = cdll.dwf elif sys.platform.startswith("darwin"): dwf = cdll.LoadLibrary("libdwf.dylib") else: dwf = cdll.LoadLibrary("libdwf.so") #print DWF version version = create_string_buffer(16) dwf.FDwfGetVersion(version) print "DWF Version: "+version.value cDevice = c_int() dwf.FDwfEnum(c_int(2), byref(cDevice)) # 2 = enumfilterDiscovery print "Found "+str(cDevice.value)+" devices" cChannel = 2 cOutput = cDevice.value*cChannel hdwf = c_int() #open device for iDevice in range (0, cDevice.value): dwf.FDwfDeviceOpen(c_int(iDevice), byref(hdwf)) if hdwf.value == 0: print "failed to open" quit() for iChannel in range (0, cChannel): print "Configure "+str(iDevice+1)+"/"+str(iChannel+1) # enable channel dwf.FDwfAnalogOutNodeEnableSet(hdwf, c_int(iChannel), c_int(0), c_int(True)) # 0 = AnalogOutNodeCarrier # configure dwf.FDwfAnalogOutNodeFunctionSet(hdwf, c_int(iChannel), c_int(0), c_int(1)) # 1 = funcSine dwf.FDwfAnalogOutNodeFrequencySet(hdwf, c_int(iChannel), c_int(0), c_double(1000.0)) dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, c_int(iChannel), c_int(0), c_double(1.0)) # set trigger source to external trigger 1 dwf.FDwfAnalogOutTriggerSourceSet(hdwf, c_int(iChannel), c_byte(11)); # 11 = trigsrcExternal1 #set different phase iOutput = iDevice*cChannel+iChannel dwf.FDwfAnalogOutNodePhaseSet(hdwf, c_int(iChannel), c_int(0), c_double(360.0*iOutput/cOutput)) # start the channel, this will wait for the trigger dwf.FDwfAnalogOutConfigure(hdwf, c_int(iChannel), c_bool(True)) # configure Trigger-1 pin to output the triggerPC signal for the last device dwf.FDwfDeviceTriggerSet(hdwf, c_int(0), c_byte(1)) # 1 = trigsrcPC # after open, before the first run wait a bit for the offsets to stabilize time.sleep(5) print "Pulse trigger to start generation..." dwf.FDwfDeviceTriggerPC(hdwf); time.sleep(60) print "done." dwf.FDwfDeviceCloseAll()
  3. I want to be able to output a .wav file. I can output a sine wave just fine from python, but I'm having trouble with this. I am loading the wav file. The array is populated. I've been looking for a funcPlay example, but I have not found any. I am able to import the file into waveforms and send it out using play. Thanks. import numpy as np import scipy.io.wavfile import matplotlib.pyplot as plt import ctypes import winsound from ctypes import * import time from dwfconstants import * import sys rate, data = scipy.io.wavfile.read('/Users/don/1.wav') plt.plot(data) plt.show() sin_data = np.sin(data) if sys.platform.startswith("win"): dwf = cdll.dwf elif sys.platform.startswith("darwin"): dwf = cdll.LoadLibrary("/Library/Frameworks/dwf.framework/dwf") else: dwf = cdll.LoadLibrary("libdwf.so") # declare ctype variables hdwf = c_int() channel = c_int(1) # print DWF version version = create_string_buffer(16) dwf.FDwfGetVersion(version) print("DWF Version: {}".format(version.value)) # open device print("Opening first device...") dwf.FDwfDeviceOpen(c_int(-1), byref(hdwf)) c_double_p = ctypes.POINTER(ctypes.c_double) data_p = data.ctypes.data_as(c_double_p) if hdwf.value == hdwfNone.value: print("failed to open device") quit() print("Generating audio...") print("Configure and start first analog out channel") print("Generating custom waveform...") dwf.FDwfAnalogOutNodeEnableSet(hdwf, channel, AnalogOutNodeCarrier, c_bool(True)) dwf.FDwfAnalogOutNodeFunctionSet(hdwf, channel, AnalogOutNodeCarrier, funcPlay) dwf.FDwfAnalogOutNodeDataSet(hdwf, channel, AnalogOutNodeCarrier, data_p, data.size) dwf.FDwfAnalogOutNodeFrequencySet(hdwf, channel, AnalogOutNodeCarrier, 44100) dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, channel, AnalogOutNodeCarrier, c_double(2)) dwf.FDwfAnalogOutConfigure(hdwf, channel, c_bool(True)) dataLost = c_int(0) dataFree = c_int(0) dataCorrupted = c_int(0) psts = c_int(0) dwf.FDwfAnalogOutNodePlayStatus(hdwf, channel, AnalogOutNodeCarrier, dataFree, dataLost, dataCorrupted) dwf.FDwfAnalogOutStatus(hdwf, channel, psts) print("psts: {}".format(psts)) print("dataLost: {}".format(dataLost)) print("dataFree: {}".format(dataFree)) print("dataCorrupted: {}".format(dataCorrupted)) while psts != DwfStateDone: dwf.FDwfAnalogOutNodePlayStatus(hdwf, channel, AnalogOutNodeCarrier, dataFree, dataLost, dataCorrupted) dwf.FDwfAnalogOutStatus(hdwf, channel, psts) dwf.FDwfAnalogOutNodePlayData(hdwf, channel, AnalogOutNodeCarrier, data_p, data.size) # if state == c_int(0): # print("state is 0") # dwf.FDwfAnalogOutNodePlayData(hdwf, channel, AnalogOutNodeCarrier, data_p, data.size) # print("Configure and start first analog out channel") # dwf.FDwfAnalogOutEnableSet(hdwf, c_int(0), c_int(1)) # print("1 = Sine wave") # dwf.FDwfAnalogOutFunctionSet(hdwf, c_int(0), c_int(1)) # dwf.FDwfAnalogOutFrequencySet(hdwf, c_int(0), c_double(3000)) # print("") # dwf.FDwfAnalogOutConfigure(hdwf, c_int(0), c_int(1)) time.sleep(10) print("done.") dwf.FDwfDeviceClose(hdwf)
  4. I try to receive data with an Analog Discovery Kit (AD) from a FPGA written with my own protocol. Three signals enter the AD: Clock, Trigger, and Data. At the rising edge of the trigger, I would like to sample 16 bits from the data synchronous to the clock (around 20 Mhz). How can this be done with an AD and SDK? With an FPGA writing this is a matter of minutes, but some how I cannot wrap my head around this. Below is the code I am using, but sadly it returns only 0x0000 or 0x000. How to receive data in this way? Cheer, VonPuffelen FDwfDigitalInConfigure(AnalogDiscoveryHandle, false, true); // start sampling STS sts; unsigned int timer = 0;// wait for receiving do{ if(!FDwfDigitalInStatus(AnalogDiscoveryHandle, true, &sts)) // pull for trigger event { printf("AcquireErro(42)"); return 42; } timer++; }while((sts != stsDone) && (timer < 0x1FFF)); FDwfDigitalInStatusData(AnalogDiscoveryHandle, data, length*sizeof(unsigned short)); // fetch data from IO buffer. FDwfDigitalInConfigure(AnalogDiscoveryHandle, false, false); // stop sampling
  5. PikeOS project on ZC702

    Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  6. 3.6.8 SDK release

    Dear Digilent, I've been exploring the 3.6.8 features and love the impedance analyzer. What's the schedule for updating the Waveforms SDK and its Reference Manual? I'm very interested in automating some impedance measurements using python. If this has been done already, I apologize for not finding and asking this question. Thanks for the awesome tool. Craig ps. here's my video I created a couple days after 3.6.8 release, Analog Discovery 2 Impedance Analyzer, OPTs and What Tube Plates Really See!!!
  7. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  8. Problem with Arty7 HDMI demo

    I'm trying to run the HDMI-in and HDMI-out demos on my ARTY Z7 board and I'm having problems building the SDK side of the projects. The problems are the same for both of these projects. After importing the project in the SDK I get the following error: 09:07:45 ERROR : The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace. As a result, this BSP will not build properly. To fix this error, please import the associated hardware project or recreate a new BSP targeting an existing hardware platform. Upon building the project I get the following errors (sorry for the Polish): Description Resource Path Location Type ../config.make: No such file or directory hdmi_in_bsp line 38 C/C++ Problem config.make: No such file or directory hdmi_in_bsp line 33 C/C++ Problem fatal error: xil_types.h: No such file or directory video_capture.h /hdmi_in/src/video_capture line 74 C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/axivdma_v6_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/coresightps_dcc_v1_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/ddrps_v1_0/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/devcfg_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/dmaps_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/emacps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpio_v4_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpiops_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/iicps_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/qspips_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scugic_v3_5/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scutimer_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/sdps_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/standalone_v6_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/uartps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/usbps_v2_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/vtc_v7_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/xadcps_v2_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [src/video_capture/video_capture.o] Błąd 1 hdmi_in C/C++ Problem make[1]: *** [coresightps_dcc_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [profile_includes] Błąd 2 hdmi_in_bsp C/C++ Problem make[1]: *** [scugic_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scutimer_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scuwdt_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [standalone_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xadcps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xddrps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdevcfg_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdmaps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xemacps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xgpiops_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xiicps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xqspips_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xsdps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xuartps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xusbps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** Brak reguł do wykonania obiektu `config.make'. hdmi_in_bsp C/C++ Problem make[2]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[2]: *** Brak reguł do wykonania obiektu `../config.make'. hdmi_in_bsp C/C++ Problem While building the project in Vivado I had some other problems which I manged to solve. I described my build below. I have followed the instructions on Digilent's reference site for the project, that is: I'm using Vivado 2016.4, I've installed the board suport files, I've cloned the demos from the Digilent github repo along with the Vivado library IP-cores I've successfully generated the projects via the tcl script with one warning, which doesn't look critical: WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_0/aRst_n(rst) Next I ran the Generate Bitstream option and got an error that the top module wasn't set. I've set the top module to hdmi_out and went through elaboration and synthesis where I got the following warnings: [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":82] [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":83] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":5] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/hdmi_in_v_vid_in_axi4s_0_0_clocks.xdc":11] [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Pfi 67-13] Hardware Handoff file hdmi_in_processing_system7_0_0.hwdef does not exist for instance processing_system7_0/inst Finally on bitstream generation I got the following error: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 6 out of 153 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DDC_scl_i, DDC_scl_o, DDC_scl_t, DDC_sda_i, DDC_sda_o, DDC_sda_t. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. I've used the fix from https://www.xilinx.com/support/answers/56354.html to ignore these rules and managed to get a bitstream. Next, following the tutorial, I've exported the hardware along with the bitstream, but the export failed because no Hardware Handoff file was found. I followed the suggestions from https://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Export-Hardware-Hardware-handoff-file-sysdef-does-not/td-p/539953 to manually generate the .sysdef file, and I managed to export the hardware and open the design in the SDK. I'm suspecting that the problem might be caused by the fact that I'm using Vivado installed by a different Windows user. I tried adding the Vivado and SDK location to the path variable, setting xilinx_sdk and xilinx_vivado variables, running the settings_64.bat scripts etc. but that didn't improve the outputs.
  9. Atlys + ISE 14.7 : HDMI demo problem

    Hi all FPGA fans and gurus ! First off : I am a total noob at all those FPGA and electronics things. So please be patient with me Now, for my problem : I recently got a second hand Atlys Board. My goal is to program it so that it can realtime rotate some hdmi input to its output. The input is a 640x480@60hz signal. The goal is to rotate it and output a 720p@60hz signal (640 pixels fit in 720, with black borders 40 pixels wide each side). So, as I don't know anything about FPGA programming, I downloaded the following EDK HDMI demo on the Atlys resource page, I thought it would be a good start to understand how hdmi inputs and outputs work with the Atlys board : https://reference.digilentinc.com/_media/atlys/atlys/atlys_hdmi_plb_demo.zip To build the project, I'm using ISE 14.7, fresh install (Windows 7). Actually I can build the project and program the Atlys with it, and even run it. However it seems it doesn't work OK. I looks like there are problem with interrupts, especially with the push buttons on the board. Wichever button I push, the callback function is never called. However, I have evidence the program does run. If, for instance, I change the main function to make it draw thing on the screen, it does it. I can also print things in the virtual terminal of the SDK. For instance, if I do a xil_printf at the beginnig of main(), things print in the terminal. However If I put a xil_printf at the beginning of the button handler function, whichever button i press nothing prints ... reason why I think it might be an interrupt problem. Needless to say that Adept button test is OK. Other thing : I'm using a fresh ISE 14.7 out-of-the-box install. I don't know if specific add-ons need installing to make Atlys work flawlessly with EDK. I might have missed some things. Especially, on the Atlys Resource page on Digilent's website, there is a zip archive and the following comment : "Atlys board support files for EDK BSB wizard. Supports EDK 13.2 - 14.7 for both AXI and PLB buses." Do I need this ? I don't have a clue about what BSB wizard is... I think all has been said =) Thanks in advance to all helpers ! Cheers
  10. Folks, I'm writing a python object for the AD2 trigger, when I set the autotimeout value with dwf.FDwfAnalogInTriggerAutoTimeoutSet isn't returned with FDwfAnalogInTriggerAutoTimeoutGet. My unittest sets autotimeout value to 1.213, get returns 1.25494304. do autotimeout values have to be some subdivided range of values? @property def autotimeout(self): v = c_double() self.dwf.FDwfAnalogInTriggerAutoTimeoutGet(self.hdwf,byref(v)) return v.value @autotimeout.setter def autotimeout(self,value): self.dwf.FDwfAnalogInTriggerAutoTimeoutSet(self.hdwf,c_double(value)) def test_autotimeout(self): self.ad2.trigger.autotimeout = 1.213 print self.ad2.trigger.autotimeout self.assertEqual(1213,int(round(self.ad2.trigger.autotimeout*1000)),"trigger autotimeout incorrect") All the other trigger variables set and get correctly. Thanks, Craig
  11. Hi, It's possible to execute the Waveforms software and in parallel execute some python script with waveforms API. I know, this can look crazy, but I'm thinking in add some physical knobs to control the values inside the Waveforms. Thanks.
  12. First Arty7 Project Program FPGA Failed

    Hi All, I have been working through the Arty - Getting Started with Microblaze project in the resource folder with the Artix-7 FPGA Development Board. When I get to step 11.2 Program the FPGA I get the following message Program FPGA failed Reason: Could not find FPGA device on the board for connection 'Local'. I have been stuck here for the last couple week and have tried several times to track down the connection issue. So far no luck. Any assistance would be greatly appreciated. Thanks, Don
  13. Hi all tagging some experts @jpeyron @attila Thank you for all the help in previous questions! From what I have gathered up till now is that I cannot access the protocol analyzers since they are at the application level and are not exposed to the SDK. However in my application I need a protocol analyzer along with the analog read of the AD2 simultaneously. (attaching previous post) So my only hope is to make a custom protocol analyzer to get the logic bitstream from the digital pins along with the raw waveform data. I tried to do the same in the code snippet attached. However the program hangs at line #79 at FDwfAnalogInStatusData. And also the logic bits i have read at this point do not reflect the right logic levels. Is there something I am missing? What is the right way to get both analog and digital data from the oscilloscope? EDIT: When it is not hanging at that line the digital values i have read from the digital pins are not the right value i am supposed to see (dont see the logic stream of the signal just half 1s and the other half 0s). How does it have to be setup to ready a signal with 500K - 1MHz signal levels? Thanks in advance! Shabbir main.cxx
  14. Arty-Z7 GPIO0 access

    Hello, I am having trouble with the last bit of my project where I have modified the video_demo of the Arty_Z7 example I added a 32bit GPIO to the Zynq7 in Vivado and exported it to the SDK. Note I am 'not' using the AXI, I am using the direct GPIO access. The .bit is automated from the block design. I have read and re-read the example in SDK for initiating a port read for this XGPIOPS Here is the code I think has an issue: (at define block and globals) #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID XGpioPs Gpio; /* The driver instance for GPIO Device. */ (at beginning of function) XGpioPs_Config *ConfigPtr; u32 InputData; (later where the code is executed) /* Initialize the GPIO driver. */ ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); status = XGpioPs_CfgInitialize(&Gpio,ConfigPtr,ConfigPtr->BaseAddr); /* Set the direction for all 32 pins to be input. */ XGpioPs_SetDirection(&Gpio, 0,0); /* Read the state of the data so that it can be verified, press any key to stop */ while (!XUartPs_IsReceiveData(UART_BASEADDR)) { InputData = XGpioPs_Read(&Gpio, 0); xil_printf("%08x\n\r",InputData); }; What this is supposed to do is blast the UART with the GPIO_0 data coming from the fabric, I confirmed on the Vivado side using ILA that the GPIO_0 data is running counters, etc as I designed it. What I actually get from the .ELF run is a constant value. I think this means I am either reading from the wrong place or I am somehow misunderstanding the function and just repeating the 32bit address of the memory location (instead of the data) Can anyone look this over and point out my error?
  15. SDK Coding

    Its been a few months since I've been introduced to FPGA design and have successfully completed some basic projects, however, while trying to effectively establish communication with devices via protocols such as uart, spi, and i2c I usually fall short. From what I understand you must enable these through the ZYNQ7 processor on block design or drop in their respective IP blocks. How to actually connect these to external devices becomes fuzzy for me and interpreting/modifying the SDK code is very difficult. In short I'm looking for some help/resources to get the ball rolling on these type of projects, and how to actually understand/develop the C code for processor myself, on both the Microzed and Zybo development boards. Thank you
  16. Hi,Just start learning HLS and XSDk. Currently I am working with number series. My goal is to print number series sequentially as for "N" times in Tera Terminal. While compiling the program codes, its returning values but it is not in sequence. Expected result:2, 4, 8, 16,32,64,128,256,512,1024, But i am getting : 4,8,16,256,128,1024,16,64,512,64, (not in order) For more details refer this [link]: https://forums.xilinx.com/t5/Welcome-Join/Returning-only-Last-value-in-XSDK-From-HLS-IP-Instead-of-series/td-p/767236 void Numberseries1(ap_uint<32> seed, ap_uint<32> &dout) { #pragma HLS INTERFACE s_axilite port=seed bundle=a #pragma HLS INTERFACE s_axilite port=dout bundle=a #pragma HLS INTERFACE s_axilite port=return bundle=a ap_uint<32> reg[10]; int result=1; int i; for(i=0; i < 10;i++) #pragma HLS unroll factor=8 if (result<seed) { result *= 2; reg =result; dout= reg; } }
  17. Hello All, I'm playing around with the "analogout_custom" C sample program that comes with the Waveforms SDK (/usr/share/digilent/waveforms/samples/c/analogout_custom.cpp). I've made some observations that don't align with my expectations. I'm hoping one (or more) of you could kindly offer some insight on what is happening. I'm running libdwf.so.3.4.7 on an Ubuntu 16.04 x86-64 machine. I have an Analog Discovery 1 and an Analog Discovery 2 wired such that ad1.aout1 --> ad2.ain1+ ad1.gnd --> ad2.ain1- I'm playing the waveform out through the Analog Discovery 1 and the "analogout_custom" program. I'm capturing the resulting waveform through the Analog Discovery 2 and the Waveforms 2015 oscilloscope. I've attached my Waveforms 2015 oscilloscope configuration file. I've also attached a screenshot of the Waveforms 2015 oscilloscope showing the results of two runs of "analogout_custom". Channel 1 (yellow) displays the waveform produced by my most recent run of "analogout_custom". Reference 1 (gray) displays a waveform that was captured on Channel 1 during a prior invocation of "analogout_custom" and saved off as a reference waveform. Expectations: 1) A waveform consisting of 4096 samples played at 10 kHz should have a duration of ~0.5 seconds. 2) The waveform should play once, given the default of AnalogOutRepeat = 1. 3) The waveform should begin playing at the first sample, which always has the same value. 4) The generated waveform should be consistent for all invocations of "analogout_custom". Unexpected observations: 1) The waveform has a duration of ~1.8 seconds, as highlighted by the cursors' delta X in the oscilloscope screenshot. 2) The waveform plays more than once, as indicated by the multiple peaks on the yellow waveform in the oscilloscope screenshot. 3) The waveform does not begin playing at the first sample, as indicated by the different values at x=0 for the yellow and gray waveforms. 4) The played waveform is not consistent between invocations, as indicated by the yellow and gray waveforms not aligning. Here's the "analogout_custom.cpp" source code for your convenience: #include "sample.h" int main(int carg, char **szarg){ HDWF hdwf; double rgdSamples[4096]; char szError[512] = {0}; // generate custom samples normalized to +-1 for(int i = 0; i < 4096; i++) rgdSamples = 2.0*i/4095-1; printf("Open automatically the first available device\n"); if(!FDwfDeviceOpen(-1, &hdwf)) { FDwfGetLastErrorMsg(szError); printf("Device open failed\n\t%s", szError); return 0; } printf("Generating custom waveform for 5 seconds..."); // enable first channel FDwfAnalogOutNodeEnableSet(hdwf, 0, AnalogOutNodeCarrier, true); // set custom function FDwfAnalogOutNodeFunctionSet(hdwf, 0, AnalogOutNodeCarrier, funcCustom); // set custom waveform samples // normalized to ±1 values FDwfAnalogOutNodeDataSet(hdwf, 0, AnalogOutNodeCarrier, rgdSamples, 4096); // 10kHz waveform frequency FDwfAnalogOutNodeFrequencySet(hdwf, 0, AnalogOutNodeCarrier, 10000.0); // 2V amplitude, 4V pk2pk, for sample value -1 will output -2V, for 1 +2V FDwfAnalogOutNodeAmplitudeSet(hdwf, 0, AnalogOutNodeCarrier, 2); // by default the offset is 0V // start signal generation FDwfAnalogOutConfigure(hdwf, 0, true); // it will run until stopped or device closed Wait(5); printf("done\n"); // on close device is stopped and configuration lost FDwfDeviceCloseAll(); } Thanks in advance! Chris (This is a repost. Original post somehow ended up in Home > Digilent Technical Forums > Scopes & Instruments > WaveForms Live and OpenScope feedback.) analogout_custom.dwf3scope
  18. DisplayPort on Genesys2 OOB project does not work

    Hi everybody I have a problem with the downloaded OOB design for Genesys 2: the DisplayPort seems to be properly configured, but the video does not appear. (It is not an issue related with the board, because the OOB stored on the flash of Genesys2 perform perfectly). I downloaded the design from the GIT (https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-user-demo/start), dated 2017 March 18. Another ZIP is available, dated today (2017 May 2), looking inside they seems equivalent. Both designs are the previous version of the OOB, updated to Vivado 2016.4 and SDK 2016.4 So, I created the Vivado 2016 project, I asked for the proper evaluation licenses, and I achieved the bitfile. without particular problems. Then, I exported the HW to SDK, and I tried to import the sdk project/BSP (g2demo and g2demo_bsp) according to the instructions. I had a lot of errors. So, I generated a brand new BSP, with all driver updated, and I compiled the application. Everything fine. I downloaded to the board, and everything performs OK.... except DisplayPort. Console messages seems ok, the presence IRQ works, the DP is correctly trained and the screen is properly configured.... and nothing is shown. (By the way, VGA and HDMI works perfectly). Console messages are reported in screen.png I noted that the BSP delivered is really,really outdated. I tried to "patch" a .mss with the same outdated versions, but I had (as expected) a lot of bugs. Difference on versions are shown in drivers.png. Then I tried to keep the brand new BSP, and to outdate only the dp driver. It compiled, fine, but the behaviour is exactly the same. Now, I have some difficulty to proceed. It seems that the BSP you deliver is outdated, and it seems very strange. May you check your distribution, or, if correct, please give me an help about how to have correct compilation. Many thanks in advance, Marco Pavesi.
  19. using fixed point design in vivado SDK

    Hello there, I have developed a fixed point design, then an IP core for matrix multiplication using vivado HLS.I need to deal with fixed point data types in Vivado SDK to send data to a fixed point IP core.Does anyone has any idea of how can i go about.?Thank you
  20. I would like to utilize the SDK to develop a C++ application for the Analog Discovery 2 within Visual Studio 2015. I am trying to get one of the C++ sample applications provided to work but I am not having much luck. I tried adding a reference to dwf.dll but that failed. There is a lib file - do I use that and how? I am not sure what type of application I should start with (Forms, Console) and how do I bring in the sample app. Has anyone this? Can you provide step by step instructions with the expected result?
  21. JTAG-HS3 connection with API (DmgrOpen)

    Hi everyone ! I'd like to use the JTAG-HS3 cable to work on a project which consists in testing several interconnections between devices on a board. I'm using DJTG and DMGR APIs and i'm connected via ssh to the computer which has the cable plugged on. My question is: How do i connect to the board with the DMGR API? I know that i have to use DmgrOpen() function but it requires a "device name", which i don't have. Thanks in advance ! Have a nice day !
  22. ZYBO - downloaded program data is wrong

    Hi guys, I bought a zybo board and did a simple hello world project to test the functionality, but it didn't work. Here's what I've done: After exporting hardware and creating sdk projects, I downloaded the bitstream & program into zybo as usual. But the board wouldn't run the program normally(It doesn't terminate and doesn't print helloworld). So I debug the board using xsdb, step by step, and find out that disassembly result is not the same as elf file displayed in SDK. xsd shows that data at 0x100000 is 0xea020049; however, in the sdk, the data should be 0xea000049, as shown in the second picture. If I keep on stpi, since it'll go to the wrong place, CPU will finally goto infinite loop. xsdb% connect tcfchan#0 xsdb% targets 1 APU 2 ARM Cortex-A9 MPCore #0 (Running) 3 ARM Cortex-A9 MPCore #1 (Running) 4 xc7z010 xsdb% fpga -f "design_1_wrapper_hw_platform_0/design_1_wrapper.bit" 100% 1MB 1.8MB/s 00:01 xsdb% targets 2 xsdb% source "design_1_wrapper_hw_platform_0/ps7_init.tcl" xsdb% rst; ps7_init; ps7_post_config; Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended) Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended) xsdb% dow "hello_world/Debug/hello_world.elf" Downloading Program -- C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf section, .text: 0x00100000 - 0x001016eb section, .init: 0x001016ec - 0x00101703 section, .fini: 0x00101704 - 0x0010171b section, .rodata: 0x0010171c - 0x00101733 section, .data: 0x00101738 - 0x00101bab section, .eh_frame: 0x00101bac - 0x00101baf section, .mmu_tbl: 0x00104000 - 0x00107fff section, .init_array: 0x00108000 - 0x00108003 section, .fini_array: 0x00108004 - 0x00108007 section, .bss: 0x00108008 - 0x0010802f section, .heap: 0x00108030 - 0x0010a02f section, .stack: 0x0010a030 - 0x0010d82f 100% 0MB 0.4MB/s 00:00 Setting PC to Program Start Address 0x00100000 Successfully downloaded C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf xsdb% mrd 0x100000 16 100000: EA020049 100004: EA040025 100008: EA00002B 10000C: EA00003B 100010: EA000032 100014: E320F000 100018: EA000000 10001C: EA00000F 100020: F92DD91F 100024: ED3F1FBB 100028: ED6D0B20 10002C: EEF11A10 100030: 00001004 100034: 00001A10 100038: FFFF1004 10003C: EFF1019E elf file contents: Disassembly of section .text: 00100000 <_vector_table>: 100000: ea000049 b 10012c <_boot> 100004: ea000025 b 1000a0 <Undefined> 100008: ea00002b b 1000bc <SVCHandler> 10000c: ea00003b b 100100 <PrefetchAbortHandler> 100010: ea000032 b 1000e0 <DataAbortHandler> 100014: e320f000 nop {0} 100018: ea000000 b 100020 <IRQHandler> 10001c: ea00000f b 100060 <FIQHandler> 00100020 <IRQHandler>: 100020: e92d500f push {r0, r1, r2, r3, ip, lr} 100024: ed2d0b10 vpush {d0-d7} 100028: ed6d0b20 vpush {d16-d31} 10002c: eef11a10 vmrs r1, fpscr 100030: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 100034: eef81a10 vmrs r1, fpexc 100038: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 10003c: eb00019e bl 1006bc <IRQInterrupt> So, the problem is, WHY is the DRAM data partially wrong??? I almost doubt DRAM works normally, but I just bought the board a week ago lol.
  23. Hi I’d like to ask – what are the valid values of idxChannel and idxNode parameters used in many SDK functions (f.e. DWFAPI BOOL FDwfAnalogIOChannelNodeStatus(HDWF hdwf, int idxChannel, int idxNode, double *pvalue); they appear very often in SDK examples but as the hardcoded values with no explanation given, so I’ve written small piece of code to investigate this issue: for (ch = 0; ch < 5; ch++ ) { FDwfAnalogIOChannelName(handle, ch, szName, szLabel); printf ("%02d - %s (%s)\n", ch, szName, szLabel ); for (nd = 0; nd < 6; nd++ ) { FDwfAnalogIOChannelNodeName(handle, ch, nd, szNodeName, szNodeUnits); if ( strlen( szNodeName ) ) { printf (" %02d - %s (%s)\n", nd, szNodeName, szNodeUnits ); } } } it produces the following output: so I’m kindly asking - where could I find these values and identifiers listed and commented in any way? Many thanks for support regards, Natasza
  24. Hi, According to the SDK docs, there are static and dynamic libraries for Windows. For my waveforms4j Java library, I'm having major issues trying to get it to work for Windows (Linux and OSX works), and I'm wondering if it has to do with the static and/or dynamic Windows libs. So my question is, why is there a static and dynamic library? Are they independent, and I could choose one or the other, or is one dependent on the other requiring me to use both?
  25. Is there a way to execute "Defined Measurement" functions on an analog input stream from inside a custom Waveforms SDK program? I'm particularly interested in running a frequency measurement from my custom application (but ideally all of the factory defined measurement functions would be available). Judging by the SDK documentation, it seems that the only way to accomplish such a feat is to re-implement the calculation by hand such that it runs against an appropriate buffer of acquired samples. I don't want to duplicate this effort unless it's absolutely necessary. Even being able to see how these functions are implemented for the internal Waveforms functionality would be helpful if they can't be made available via the SDK API (apparently these implementations are kept secret; they are not visible in the measurement "Edit" window). UPDATE: I've established that the measurement functions are available from the Javascript API. Is it possible to boot a headless Waveforms and immediately execute a Waveforms "Script"? It doesn't seem to be possible execute a Waveforms "Script" from the normal Waveforms SDK; this would be really useful. But something along the lines of this would be great: /usr/bin/waveforms --run /path/to/MyCoolCustomScript.js where the script file is just a normal Waveforms "Script" like what you would run from the Script device.