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Found 1 result

  1. Hello All, Just joined the forum, I just received my Arty board, and ported a very simple 32 bit counter design that drives LEDs (slower bits). I can synthesize and implement the design (no warnings), I can view the schematic and it looks exactly like the RTL, however, when I try to load it onto the target I get the following warning: WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. The board does nothing! I use this exact same code on another FPGA board (Altera Cyclone-5) and it works fine... I'm assuming that the above warning is critical because after the download the boards doesn't do anything Thanks for any help! -Paul