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Found 4 results

  1. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling r
  2. Hello, I have seen a lot of contradictory information online regarding the sampling frequency of the Analog Discovery 2 ADC channel. Is it possible to sample at around 30 MHz for 20s and store the data in a csv for example with a time stamp? Second Is it possible to run several processes on the board simultaneously such as: 1) 2x analog read and data storage 2) motor control 3) Waveform generator assumming I have enough cores on my computer to run there respective programs.
  3. Hello, For a project in one of my courses my adviser asked me to find a way to control the sample rate and record length in the Analog Discovery in order to understand how to use the FFT module. Thank you, cjobi247
  4. Hi. I would like to know, if it is possible to modify the sampling frequency, the number of samples of the ADC of the card Nexys 4 DDR ?. I know there are modes of use, but these depend on the registers but do not allow manipulation of these parameters. If you can, I would be grateful if you could tell me how it is possible.