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Found 4 results

  1. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
  2. Hello, I've been working on a project that I need to use the ip integrator and add an RTL block that I made. I'm using a Basys 3 board, Vivado 2018.3 and MicroBlaze ip. I was trying to add the RTL to the source and to the diagram and I used the getting started with ip integrator tutorial. The tutorial itself worked fine and when I added the RTL It passed the validation, synthesis, implementation and even generating the bitstream but then I couldn't export hardware for programing the MicroBlaze and it gave an error saying "Cannot write hardware definition file as there are no generated IPI blocks". Correct me if I'm wrong, but I understood that I need to create an ip that contains my RTL project and only then I can add it to the diagram. If so, does anybody have a tutorial of how to make a new ip? and if that is not the case, what do you think is the problem? thank you, Netanel.
  3. hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values md5.txt1.txt pancham_round.txt
  4. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here