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Found 9 results

  1. Does the demo design (Zybo-Z7-20-HDMI-2018.2-1.zip) support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  2. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The compu
  3. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my
  4. Hello, I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE. Intention: To demonstrate whether the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS. Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used th
  5. Hi I am back to working with customizing the rgb2dvi IP. As mentioned in an earlier post, I made the changes in .vhd files, and I set the compile order of the .xdc files. I wrote a simple video generator (which also outputs the appropriate timing signals to the IP) in verilog, and a 'top' module that connects the two together. The design needs an external clock, which I will supply and I found which pin I need to use to get a universal clock. I have two questions: 1) The IP as a asynchronous reset, and the documentation says 'Asynchronous reset of configurable polarity. Assert,
  6. I have two questions 1) According to Digilent documentation, the rgb2dvi IP is designed to take a minimum pixel clock of 40 MHz. My video data is at 27 MHz, so it seems to me that I will have to go into the original source code and try to make it work for a lower pixel clock When I open the src folder of the IP, I open the rgb2dvi.vhd, which is the 'top module'. From there, all the parameters are taken. See line 66- There are 3 options given kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3) This parameter is taken
  7. I am using the rgb2dvi IP of digilent, and I wanted to know exactly how to use the pHSync, pVSync, and pVDE signals that it requires as an input I can understand that pVDE is high for the duration of active video, and low for the duration on non-active video For pHSync, is it high for the duration of the horizontal sync? Or does is it a single clock long? Does it go high on the same clock as pVDE goes low? For pVsync, the same questions apply. Also, every end of a frame is also the end of a line, so do both pVSync and pHSync go high at the end of a frame? Basically, my que
  8. This question came up on a previous thread and I wanted to ask it separately According to the Digilent rgb2dvi IP specs, "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" My video is 720x576, with a 27 Mhz pixel clock, which is not supported as is In the previous thread, @hamster said that it is possible to customize the IP by changing the divide-by values in the clkgen. Can someone help me with this? Has anyone ever had a similar problem? Also, how will I deal with the lower pixel resolution?
  9. Hi everyone, Currently I am working with Genesys 2 board. My sensor output is 12-bit each component. My output design is attached below. I am using HDMI output. I collect the rgb2dvi IP form the "HDMI example". But the problem is that it only supports 8-bit input component. So, I have to convert output 12-bit component to 8-bit component at "AXI_video_out" IP. But, I think this type of convert mechanism degrading my output image quality. How can I convert the "vid_pData[23:0]" to "vid_pData[39:0]" at "rgb2dvi"? Any suggestion will be really helpful. Thanks Rappy