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Found 9 results

  1. Does the demo design ( support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  2. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 2475.248 MHz (CLKIN1_PERIOD, net CLK) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y1 (cell hdmi_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (6.059999), multiplication factor CLKFBOUT_MULT_F (15.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. To get around, I edited the rgb2dvi_ooc.xdc such that I have commented out the following: #create_clock -period 6.060 [get_ports PixelClk] #create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] But it didn't help. What more can I do? Suggestions, advises? I have attached the top level xdc. hdmi_vdma.xdc
  3. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my laptop (Lenovo Z710 Ideapad running Windows 8.1) and my TV (Toshiba 49L420U with dimensions 1920x1080) After consulting a lot of posts on this website, especially this one and this one, I’m still not sure about what the magic formula is to get these IP blocks to work. The posts don't seem to be addressing the problems I'm having with this design, but rather making changes to the specific implementation of the project. They were all older versions of the IP blocks and vivado, and they were using different boards, so those factors may have contributed to why those examples didn't work for me. I’ve reduced my critical warnings down to three, which are the following: 1.) Timing: i get the following timing warnings after running implementation 2.) Set_property expects at least one object a. I get two of these, for the two constraints listed at the very bottom of the constraints I showed in the first image above. How can I write these constrains such that Vivado will recognize them and won't throw a warning? I read from the posts I mentioned earlier that timing requirements may throw a critical warning but the design will work anyway, but I haven't had the same fortune. So has anybody here gotten their design to fit timing and create a working project? If so I'd love to know how, and if you failed timing but still got the project to work, what did your timing analysis look like? As can be seen in the block diagram, I pulled the aPixelClkLockd signal out to an LED, which is an active high signal. But I haven't gotten this signal to be high, so obviously that's a problem. If the clock recovery block in the dvi2rgb IP can't get a lock on the incoming clock signal, does this mean that the project is not properly constrained, or does this mean that the IP block won't work with my laptop? I read a lot about DDR signals, and I believe that I set those up correctly in my block diagram and constraints file. But I didn't understand what hpd signals did, and I don't know which block diagram they are supposed to come from. Any help here would be greatly appreciated! Best, Ben
  4. Hello, I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE. Intention: To demonstrate whether the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS. Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used the diligent dvi2rgb and rgb2dvi IPs. Have used a PLL (not MMCM) to generate the ref_clk (125MHz is board input and the PLL produces the 200MHz clk required delay taps). I have attached my top level VHDL file which shows the connections. I have also attached the XDC file. Note that in the XDC I have changed the tmds_rx_clk frequency to 80MHz which is suitable for a HDMI data source with 720p resolution (else there will be Impl errors as the Z7-10 has a -1 speed grade FPGA). Bit stream was successfully generated without timing errors. The synth design is as shown below. The design is not working after I have downloaded the bitstream. So the most important question is if the above makes sense? If the above is rubbish, then what can I do to improve my design? I just want to pass HDMI data from Rx port to the Tx port. Do I need to do some buffering of the pixel data (3 FIFOs for each channel with 8bits width, depth - I don't know ) before connecting vid_pData from dvi2rgb to rgb2dvi? Else what would help? Any help/suggestions are appreciated. Regards. hdmi_pass_top.vhd hdmi_pass.xdc
  5. Hi I am back to working with customizing the rgb2dvi IP. As mentioned in an earlier post, I made the changes in .vhd files, and I set the compile order of the .xdc files. I wrote a simple video generator (which also outputs the appropriate timing signals to the IP) in verilog, and a 'top' module that connects the two together. The design needs an external clock, which I will supply and I found which pin I need to use to get a universal clock. I have two questions: 1) The IP as a asynchronous reset, and the documentation says 'Asynchronous reset of configurable polarity. Assert, if PixelClk and SerialClk are not within spec.'. The comment next to the source code itself says 'asynchronous reset; must be reset when RefClk is not within spec'. Can someone explain exactly what this means in simple English? I could not find any signal called 'RefClk' in the design. Practically, what should I do with the reset? 2) I attached a picture of the synthesis schematic from Vivado. Now, my video generator has a video data output of 24 bits (3 8 bit RGB values), and the IP has a video data input of 24 bits. So what are the D and Q signals coming out of the video generator, and why are they 2 bits each?
  6. I have two questions 1) According to Digilent documentation, the rgb2dvi IP is designed to take a minimum pixel clock of 40 MHz. My video data is at 27 MHz, so it seems to me that I will have to go into the original source code and try to make it work for a lower pixel clock When I open the src folder of the IP, I open the rgb2dvi.vhd, which is the 'top module'. From there, all the parameters are taken. See line 66- There are 3 options given kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3) This parameter is taken to line 118, where it is fed into the ClockGen. It is interesting that the comment there says that the ClockGen can actually take 5 options kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5 And finally, inside the ClockGen.vhd file line 36 declares the parameter kClkRange, and confirms that it can take 5 options. But whatever is declared here is superceded by what is declared in the top module kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5 So although the ClockGen clearly has five options,it seems that the IP itself is limited to three. Can someone please explain why and what will happen if I write '5' for kClkRange? 2) I now have to take these design files and add them to a new project in Vivado. I see that in the src folder of the IP, there are also three xdc files, and two of them actually have real code in them. What should I do with them? I plan on using a different xdc file to assign the pins on my board.
  7. I am using the rgb2dvi IP of digilent, and I wanted to know exactly how to use the pHSync, pVSync, and pVDE signals that it requires as an input I can understand that pVDE is high for the duration of active video, and low for the duration on non-active video For pHSync, is it high for the duration of the horizontal sync? Or does is it a single clock long? Does it go high on the same clock as pVDE goes low? For pVsync, the same questions apply. Also, every end of a frame is also the end of a line, so do both pVSync and pHSync go high at the end of a frame? Basically, my question is how these signals work together, and what they expect to be "fed"
  8. This question came up on a previous thread and I wanted to ask it separately According to the Digilent rgb2dvi IP specs, "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" My video is 720x576, with a 27 Mhz pixel clock, which is not supported as is In the previous thread, @hamster said that it is possible to customize the IP by changing the divide-by values in the clkgen. Can someone help me with this? Has anyone ever had a similar problem? Also, how will I deal with the lower pixel resolution?
  9. Hi everyone, Currently I am working with Genesys 2 board. My sensor output is 12-bit each component. My output design is attached below. I am using HDMI output. I collect the rgb2dvi IP form the "HDMI example". But the problem is that it only supports 8-bit input component. So, I have to convert output 12-bit component to 8-bit component at "AXI_video_out" IP. But, I think this type of convert mechanism degrading my output image quality. How can I convert the "vid_pData[23:0]" to "vid_pData[39:0]" at "rgb2dvi"? Any suggestion will be really helpful. Thanks Rappy