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Found 5 results

  1. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling r
  2. When changing the start and stop frequencies of the spectrum analyzer the resolution does not seem to change. I'm using the software in the demo mode. Is this how the actual software works. One would hope that the resolution frequency would decrease (become a smaller frequency) as the frequency span is decreased. Thanks, for any responses.
  3. czajak

    Vmodcam problems

    Hi, I am using vmodcam and have problem with image resolution and bad pixels. I have microZed 7010 board and I/O carrier and try to send image via Ethernet. First problem is, I set all the register values mentioned in the rm (https://reference.digilentinc.com/_media/vmodcam/vmodcam_rm.pdf) to get image with resolution 1600x1200 px. Unfortunately I got image containing 4 frames with resolution 800x600 px (attachment: bad_res_image.jpg). Before logging image I saw values in these registers via I2C and everything in the register is set as in the rm. Do you have any idea what is wrong?
  4. This question was posted on YouTube: Does the Nexys Video have the ability to ingest/output [email protected]? Thank you, Digilent Studio
  5. yasirshah

    Vmodcam resolution

    I am using Digilent Atlys board and Vmodcam in a project. Vmodcam have 1600*1200 maximum resolution. it can be used with 640*480 resolution. I want to know that what is the minimum resolution of Vmodcam. Can it be used for 300*200 resolution?