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Found 5 results

  1. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling rate. If I am not wrong the FFT resolution should be 961.54*10^3/4096 (for a 4096 point FFT). Backtracking from the scope, it appears that there is an offset from the expected sampling rate. Example: While 23.5 KHz is expected to fall in the 100th bin it falls in 111th bin. The sampling rate (computed from the FFT resolution formula - observing output) would be around 870 KSPS. Question 2) Would the sampling rate change if I use a 50 MHz DCLK clock instead of 100 MHz? The IP core indicates that the actual sampling rate would be 961.54 KSPS (same as that with 100 MHz clock) but I observed a shift in FFT output yet again. This time the sampling rate (computed from the FFT resolution formula) falls around 835 KSPS. Please help! P.S. - In my design I used a AXI-4 stream register slice as a pipeline stage to account for latency involved in multiplication and addition operations on the FFT output so that the signals from xfft_0 appear at the same time as the data. Frames are sent at the same rate (100MHz) at which the FFT is operated => BRAM read frequency = FFT CLK = 100 MHz. 3) Question on FFT: My FFT output appears to be almost as expected (except for the constant offset in frequency bins). After every 4095th bin there is a repetition of bin value 4080, (for a certain interval, until next 0) and I with a peak at this value. I do not understand the reason behind this. Please provide some insight on this as well.
  2. When changing the start and stop frequencies of the spectrum analyzer the resolution does not seem to change. I'm using the software in the demo mode. Is this how the actual software works. One would hope that the resolution frequency would decrease (become a smaller frequency) as the frequency span is decreased. Thanks, for any responses.
  3. czajak

    Vmodcam problems

    Hi, I am using vmodcam and have problem with image resolution and bad pixels. I have microZed 7010 board and I/O carrier and try to send image via Ethernet. First problem is, I set all the register values mentioned in the rm ( to get image with resolution 1600x1200 px. Unfortunately I got image containing 4 frames with resolution 800x600 px (attachment: bad_res_image.jpg). Before logging image I saw values in these registers via I2C and everything in the register is set as in the rm. Do you have any idea what is wrong? Second problem is more serious. In this link I send the results when I show only 800x600 px of the image ( - in 70% of cases the image I get is wrong (picture 3, 4 in the link) - in 10% of cases the image I get is shifted in some places and but we can recognize the shape (picture 5 in the link) - in 20% of cases I get image which is OK (picture 1, 2 in the link) But in 100% of cases my image have bad pixels. I would really appreciate any help or even only a hint. Thank you in advance! Best regards czajak
  4. This question was posted on YouTube: Does the Nexys Video have the ability to ingest/output [email protected]? Thank you, Digilent Studio
  5. yasirshah

    Vmodcam resolution

    I am using Digilent Atlys board and Vmodcam in a project. Vmodcam have 1600*1200 maximum resolution. it can be used with 640*480 resolution. I want to know that what is the minimum resolution of Vmodcam. Can it be used for 300*200 resolution?