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Found 4 results

  1. rob2018t

    Arty Z7 and Reset

    Hello fellow Digilent Members, I hope everyone is well. My Skill Level: I'm slowly progressing my knowledge of FPGA and Vivado using the Digilent Arty Z7-20 and Arty S7-50. Essentially quite a beginner and I've created simple RTL designs to flash LEDs, utilised the Microblaze, Zynq and made a AXI-4 IP block. All really exciting stuff IMO...I just need to make something more useful now. My Question: when designing with the Arty S7-50 I'm able to specify the board and then drag across the reset into my top diagram and/or utilise that when auto completing the design. However in the
  2. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am
  3. Hello all, I have a Nexys4 DDR and I want to reprogram it, as it's done with "PROG" button. As example I want to connect the IPROG/Program_B signal to be triggered when something happens like the output of my circuit is "1", or using a switch. How can I do that? I've read documentation about multiboot but I don't want to load two bitstreams, only one and reprogram the FPGA with it when I want. I suppose that using the Program_b signal is the way to go but I don't know how I can use it. Some code, tutorial or documentation would be appreciated. Thank you
  4. I am working with the Block Design flow in Vivado 2015.3. I don't seem to be getting how to connect the reset system. My design keeps acting like the clock is being held in reset. When I look closely it appears that the reset signal on the Arty is active low while the reset module in the design expects active high. What am I missing here? Michael Harpe