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I'm trying to write a script to custom define signals on the Patterns tool by following the code in the reference manual. However, these are not working: Patterns1.Channels.DIO1.name = "Testing" <- Doesn't change the name of the signal, but once I click on the edit button the pop window shows it as "Testing". Once I run the program a second time it get an error for "Patterns1.Channels.DIO1.name = "Testing"" and it's not resolved until I change it to "Patterns1.Channels.Testing.name = "Testing"" Patterns1.Channels.DIO1.DIO.value <- Returns: " Result of expression 'Patterns1.Channels.DIO1.DIO' [undefined] is not an object." Additionally, the reference manual doesn't show how to automatically set up the signals from the start using the script. For example, how to select the output as PP or Type as Custom. Do I have to set this up manually every time? Thank you in advance!
The "Nexys Video™ FPGA Board Reference Manual" (Revised May 30, 2017) describes in Table 9 (page 20) the "Recommended usage" of the pins of JXADC with "LVDS_25 input/output" (with V_ADJ=2.5V). However, the discussion in has led to the result that LVDS-standard is not supported without changing the board. I would recommend to change the reference manual at this point. The documentation should clearly name supported standards especially if it is targeted to students that may not know all details of the IO-standards. The best way of a replacement of "LVDS" would be a list of IO-standards that work on this connector without changing the board. If the list is too long (the list of standards supported by Artix-7 fills several pages) it can be moved to the appendix. The minimal solution would be the replacement of "LVDS" by "differential" and let to the user/student to find out if a certain standard can be implemented with the board. Btw. There is a small typo in the table: The 3rd differential pair of JXADC is 3-9 (according to the schematic).
Hey, In V4 version of the doc (and board?), http://digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V4.pdf (currently linked on Digilent website), the pin constraints for pcie-rx3_p, pcie-tx3_p, pcie-rx3_n and pcie-tx3_n are wrong, as they are the same as pcie rx/tx port 2 (see first half of page 19 of aforementioned pdf). In V3, https://www.digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V3.pdf (found via Google), I discovered what might be the correct values - it would be nice if someone could confirm them as being right (page 19).