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Found 3 results

  1. I'm stumped and have been pouring through the posts in these forums over the last couple of days but can't quite get to a solution. I know this has sort of been beaten to death...so take it easy on me. I'm trying to get the Arty A7-100T board to boot from SPI flash on power-up. I'll try to go in the order of which I've configured things as concisely as possible...any insight or help is much appreciated. IP block in Vivado is customized as shown in image below. In addition, I've connected 'ext_spi_clk' to a 50MHz clock generated by the clocking wizard. Bitstream generates successfully and design is exported to SDK. I've run numerous applications out of BRAM and DDR3 via the normal microblaze bootloop (i.e. no flash) so I know the system is configured correctly to some degree. I've tried this both WITH and WITHOUT a compressed bitstream as noted in the tutorial here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start I generated the BSP with xilifs library v5.12 and set 'serial_flash_family' to 5. I then created a user application with a modified linker script to run out of DDR3. I verified this works just fine in the standard microblaze bootlop as noted above. I generated the 'srec_spi_bootloader' application. I originally set the memory location to 0x00C00000, but have since used 0x00300000. Complied the application with no issues. I then generated a bitstream as indicated in the tutorial with the 'srec_spi_bootloader.elf' set to initialize in Block RAM. Followed the steps for programming flash - first loaded the user application at the memory offset that matches the compiled 'srec_spi_bootloader' application (so 0x00300000). Then programmed the generated bitstream at offset 0x0. Originally, I had the wrong memory part selected and have had difficulty finding any documentation that points to the updated part. Ultimately just read the letters on the actual part itself and found that 's25f128sxxxxxx0-spi-x1_x2_x4' worked. So that's what I've been using. After programming and power cycling, I see the DONE LED illuminate but nothing happens. There's been some tweaks to the process here and there, but this seems to be the most convincing order of operations I've been able to find on the web. As an interesting side note, I can load the flash memory with the application at 0x00300000 and run the 'srec_spi_bootloader' out of the microblaze bootloop when it's set to initialize in Block RAM and it loads the application just fine. It's just when I add the step of writing the full bitstream to offset 0x0 that it fails to actually run the application on power-up, despite the fact the green DONE LED illuminates. Any thoughts???? 💡💡💡
  2. Hi all, I'm confused about storing bitstream into the SPI memory that is on board and how to use a SPI bus to interface external peripheral. To be more specific if I need to use the on board SPI memory (IC3 on the schematic board) to store my bitstream I've to add the AXI Quad SPI attached to my Microblaze or this memory is adreessed automatically from the FPGA at startup? If instead only use the on board SPI memory to store my bitstream and then autoconfig the FPGA on startup I need to drive external SPI peripheral (e.g. and DAC) I've to add the AXI Quad SPI and then drive it from Microblaxe through the AXI mapping? I'm a little confused about this point... [EDITED] I'm reading again the Cmod A7 manual (MANUAL) and I've found some information into the paragraph 2.2 and Chapter 4. if I've correctly understand I can use the SPI memory to store my FPGA program without need to instantiate the AXI Quad SPI bus because this task will be do automatically on the FPGA startup (this sound also logic if I've a design that not need of a microblaze core, lika a simple logic as the button example, provided from Digilent), but if I need to store some data into the SPI memory, e.g. configuration data for my application I can read the SPI through the Microblaze into the adreess not used for the bitstream, my think is correct? Also if I need to use an external peripheral different than the on board memory (like a serial DAC) I'll use another AXI Quad SPI bus and then set the physical FPGA outputs for it through the XDC filles, e.g. using some pio pins. Is correct? Make sense? Thank!
  3. Hello, I'm having some issues with multiple (16bit) transactions while holding slave select low. I'm using the example master polling spi code from the xilinx SDK, and have manual slave select working where it holds the SS line low while performing the multiple transactions, and once finish it goes high again. My issue is that i'm trying to make a simple slave which can write to a register continuously if it receives a write command from the master, and then if a read command is sent from the master, the slave will send back whatever is in the designated register requested by the master. Is the data transmit register also a double buffer? My main objectve is to receive the read command, and start transferring the data on the next group of SCK pulses but right now it seems to be delayed by two transactions. The image attached shows more of what i'm trying to accomplish. the high bit of the 16 bits is a read/write(1 is write, 0 is read) command, and the lower bits are a register address. so the final result of the first 3 transactions should result in register 5 having the value (0x8009), which it does, but when the next transfer happens, the 0x0005 command should be indicating a read of register 5 and output on the miso line 0x8009 on the 2nd transaction (i.e. when MOSI is 0x0007 i want MISO to have 0x8009). Also this is my current code: /***************************** Include Files **********************************/ #include "xparameters.h" #include "xstatus.h" #include "xspi_l.h" #include "xil_printf.h" /************************** Constant Definitions ******************************/ /* * The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily * change all the needed parameters in one place. */ #define SPI_BASEADDR XPAR_SPI_0_BASEADDR /**************************** Type Definitions ********************************/ /***************** Macros (Inline Functions) Definitions **********************/ /************************** Function Prototypes *******************************/ /************************** Variable Definitions ******************************/ /* * This is the size of the buffer to be transmitted/received in this example. */ #define BUFFER_SIZE 16 /* * The buffer used for Transmission/Reception of the SPI test data */ u16 Buffer[BUFFER_SIZE]; /* * This buffer is used to simulate a register bank. */ u16 regBank[64]; /******************************************************************************/ /** * This function is the main function of the SPI Low Level example. * * @param None * * @return XST_SUCCESS to indicate success, else XST_FAILURE to indicate * Failure. * * @note None * *******************************************************************************/ int main(void) { //int transferCounter = 0; u32 BaseAddress = SPI_BASEADDR; u16 addressMask = 0; u32 StatusReg = 0; u32 NumBytesRcvd = 0; u32 NumBytesSent = 0; u8 addressFlag = 0; u16 tester = 0; //Enable GIER XSpi_WriteReg(BaseAddress, XSP_DGIER_OFFSET, 0x0/*XSP_GINTR_ENABLE_MASK*/); for(int i = 0; i < 65; i++){ regBank = 0xBEEF; } for(int i = 0; i < BUFFER_SIZE; i++){ Buffer = 0x0; } //Configure IPIER XSpi_WriteReg(BaseAddress, XSP_IIER_OFFSET, 0x0 /*XSP_INTR_SLAVE_MODE_MASK | XSP_INTR_RX_OVERRUN_MASK | XSP_INTR_RX_FULL_MASK | XSP_INTR_TX_UNDERRUN_MASK | XSP_INTR_TX_EMPTY_MASK | XSP_INTR_SLAVE_MODE_FAULT_MASK | XSP_INTR_MODE_FAULT_MASK*/); //Configure SPICR XSpi_WriteReg(BaseAddress, XSP_CR_OFFSET, XSP_CR_ENABLE_MASK); //Write data to the SPI DTR XSpi_WriteReg(BaseAddress, XSP_DTR_OFFSET, 0xDEAD); xil_printf("setup registers hi\r\n"); while(1){ if(NumBytesRcvd == 4){ for(int i = 0; i < BUFFER_SIZE; i++){ xil_printf("buffer: 0x%x regBank: 0x%x addressmask: %d\r\n", Buffer, regBank , addressMask); } } NumBytesSent = 0; NumBytesRcvd = 0; addressMask = 0; if((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_SLAVE_MODE_MASK) == 0){ /* * Fill up the transmitter with data, assuming the receiver can hold * the same amount of data. */ while ((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK) == 0) { XSpi_WriteReg((BaseAddress), XSP_DTR_OFFSET, Buffer[NumBytesSent++]); } /* * Wait for the transmit FIFO to transition to empty before checking * the receive FIFO, this prevents a fast processor from seeing the * receive FIFO as empty */ while (!(XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_TX_EMPTY_MASK)); /* * Transmitter is full, now receive the data just looped back until * the receiver is empty. */ while ((XSpi_ReadReg(BaseAddress, XSP_SR_OFFSET) & XSP_SR_RX_EMPTY_MASK) == 0) { Buffer[NumBytesRcvd++] = XSpi_ReadReg((BaseAddress), XSP_DRR_OFFSET); } if(Buffer[0] & 0x8000){ addressMask = Buffer[0] & 0x00FF; regBank[addressMask] = Buffer[0]; }else{ addressMask = Buffer[0] & 0x00FF; XSpi_WriteReg((BaseAddress), XSP_DTR_OFFSET, regBank[addressMask]); } } } for(int i = 0; i < BUFFER_SIZE; i++){ xil_printf("buffer: 0x%x regBank: 0x%x addressmask: %d\r\n", Buffer, regBank , addressMask); } } Greatly appreciate the help! Nystflame