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Found 1 result

  1. Greetings everyone. I'm Samuel A. Falvo II, creator of the Kestrel-3 home-brew computer project. I'm currently using the Nexys-2 board as a development platform, since that's a known-working software/hardware configuration for me. My plan is to migrate to something different/better after I get a working reference model here. Related to this project, I'm completely ineffectual at getting the PSRAM chip to function. I was wondering if someone else has created a 16-bit Wishbone(-compatible/-like) interface to the PSRAM chip that I can re-use in my MPLv2-licensed project. After a month of trying to hack my own, I've come to the conclusion that my PSRAM chip is utterly dead on arrival: When in asynchronous mode, I could never get the chip to respond to memory writes beyond a certain (and seemingly completely unpredictable) point. But, it could read OK, as evidenced by a stable image of noise on my monitor (video refresh is configured to use external memory). When in synchronous mode, I'm utterly unable to get the PSRAM chip to drive the DQ pins when trying to read from the chip. As a result, video shows a stable pattern of pixels corresponding to the last 16-bit word written out to memory (since this precharges the DQ lines, the video circuit sees this state and treats it as valid pixel data). It is completely unknown if it's actually responding to write transactions. I just don't know, and honestly, I'm getting rather desperate now. So far as I'm able to tell, I'm well within the timing parameters of asynchronous and (especially) synchronous mode operation. If there's an existing design I can re-use to sanity-check my design, that would be especially helpful. Thanks in advance.