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Found 17 results

  1. Nadav sholev

    Basys3 USB power not working

    Hello, I just opened my new basys3 board (novice EE student). As per the documentation I tried to power the board via usb-b (port j4) first through a laptop usb then through a 5v 2A charger making sure the jp2 jumper was set on usb and jp1 to the spi flash test program but the board did not turn on (not even the power good led). Trouble shooting that I performed: 1. Changed cable twice (didn't work) 2. Changed charger and usb ports (didn't work) 3. Powered board from external 5v power supply - the board worked perfectly. My question is could the smd soldering be defective, where can I mesure the voltage provided by the usb? Thank you for your help, If there is any more information I can provide please let me know
  2. Hi What is the typical power consumption of cmod s7 board ?
  3. Power Control

    Data logging

    we currently have the analogue discovery unit we are trying to set up a data logger to allow us to measure frequency at 3dp eg 50.124hz at 100ms for 35 minutes but the maximum seems to be 18 minutes but we can get round this by writing java script ? we also want to measure an analogue input to convert as a MW value. in the maths function we would like to work out the script to allow us to convert 10v to say 11KV? a binary triger to set the logger to start recording. but where struggling with script who can we chat to on here to assist me where 60% there
  4. ethan.schweinsberg

    JTAG-SMT2 Power Consumption

    I am looking to use the JTAG-SMT2 module in a design. After reading the reference manual, I am noticing that there is no spec for power consumption. I need to know the maximum current draw of the device. Can anybody help me figure this out? Thanks!
  5. lowuze

    TPS65400 on PYNQ-Z1 board

    Hello! I bought PINQ-Z1 and I liked your solution, to use as a power supply chip TPS65400. I decided to use this chip in my solution. Could you explain how you calculated the values of the elements of the compensation scheme for TPS65400 (C167, C168, C172, C173, C179, C180, C184, C185, R252, R255, R262, R265). Thank you!
  6. It appears that the AD2 power supply selection does not automatically switch to external power when plugging it in after it has already been connected via USB. 1. Connect the AD2 via USB cable 2. Start waveforms2015 3. Connect external power supply(5V -3.5A) From time to time a failure appears like DptiIO failed ERC: 0xA. On Linux this issue is made worst by the fact that it appears a lot more often than on Windows even in the middle of operation of the device. This appears even without the external power supply. Something similar appears on Linux saying that the USB port did not provide sufficient power. Even if the power supply is connected later on, the issue still appears. The only way to solve this is completely disconnect the USB cable, plug in the power supply cable, then plug in the USB cable. The version of Waveforms2015 used is 3.5.4 64bit. On both Windows 7 and Linux the same version is present.(with the latest ADAPT software installed on Linux). The device is put in mode 4 with only Logic and Patterns enabled and memory allocated for them. Is there any way to solve this? Thanks
  7. khiz

    Zybo won't power on

    Hello, I have a zybo board that wont power on. I have tried to power it with an external power supply as well as with a usb cable. i would appreciate if anyone could provide me with some trouble shooting tips. I am a student and need the board for my project. it worked previously but it just wont work now. (PGOOD doesn't turn on)
  8. lvoudour

    Arty XADC power supply monitor

    Hello, I got an Arty board about two months ago and I'd like to use the power supply monitor feature. My main question is: "what's the appropriate sampling rate" Never used a 7 series FPGA before so I started reading through the XADC user guide [UG480] and the Driving the Xilinx Analog-to-Digital Converter [XAPP795] note. From what I understand (correct me if I'm wrong): Both inputs must be set to unipolar The XADC should be operated in simultaneous sampling mode to sample both voltage and current at the same time No auto-calibration in this mode. Calibration is done once at power-on The sampling rate should be low enough to cover the settling time of the analog input Looking at the respective circuit and assuming 12-bit accuracy, the settling time for the voltage sensing inputs [XAPP795,pp.2-8], [UG480,pp.79-80] is roughly tset = 9.01 * (8.33K + 8.25K + 1K + 1K) * 10nF ~= 1.67ms which implies sampling rates < 600 samples/sec if I don't want any gain errors. That's fine, but the problem is the XADC cannot be used for other, faster inputs we can't directly drive the XADC with the 100MHz board clock anymore, because the maximum ADCCLK divisor of 255 implies a minimum ~15Ksps/sec rate (not that big of an issue, plenty of PLLs in the chip - just worth mentioning) The few options I see are: Forget about mixing monitoring and higher rate signals in the same design Lower the bit accuracy and use averaging Live with the error at higher rates and use averaging Am I missing something here, do I have this whole thing completely wrong? Has anyone successfully used the monitor inputs in the Arty? (couldn't find anything online) Thanks, Lymperis
  9. jpo

    Arty current supply measurements

    Hello, I have a question about the current supply measurement circuit: Why the REF pin of the INA199 is connected to a resistive divider? The REF voltage is obtained dividing the 3.3V with resistors of 6.34K and 100 Ohms. Is it possible to tie REF to GND? Thanks!
  10. Hi, I'm reviewing Waveforms 2015 on Mac. I'm looking at the power supply window and had a few questions. 1. Is it possible to do 3.3V? I see 3V and I see 4V, but not the option to select 3.3V. 2. If I have an external power supply, can the AD2 do more than 5V?
  11. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here
  12. jude

    ZedBoard VCCAUX vs. VCBATT_0

    I am working on a solution to power the ZedBoard's BBRAM with a battery when the 12V supply is unavailable. Looking at page 28 of the HW UG, I only see VCCAUX which leads me to believe that the battery is powered by VCCAUX when the board is plugged in and switched on. On sheet 10 of the schematics I see VCCAUX and VCCBATT_0 both supplying powering the 1.8V rail. What I want to know is the following: If I connect a battery to BBRAM, will power be drawn from the battery at all times or only when the 12V supply is switched off? Please let me know if you need any more information to answer this question. Thank you!
  13. Hello everyone, and thanks in advance for reading this! On a current project, I’m working with a network of Arduino UNOs R3, each with an AnalogShield installed (to be precise, it’s 4 Arduinos+AnalogShields total, communicating over I2C). I immediately found a problem when I connected all their Vin ports together to a 12V power supply: they sourced too much current (my main power supply was reading more than 1 A!). So I quickly stopped that and tried connecting the 5V ports together to a 5V power supply. At first this was OK, but soon they started to source too much current again. I also tried powering one of them via USB and connecting all the 5V ports together… This works most of the time, but some times the 5V line’s voltage oscillates badly or they start sourcing too much current again... It's funny because sometimes things seem to work, and then stop working. I checked the health of all Arduinos and they are perfect. And I checked powering all Arduinos by themselves (no shields) both through their Vin and 5V ports, and that works with no issues... So it must be an issue with the AnalogShields... For the moment, as a temporary measure, I’m powering all of them independently through their USB ports, and connecting only their grounds together. But in my final configuration I’d like to be able to power all of them with a single power supply. Can anybody point to where the issue could be?
  14. MattW

    ZedBoard DDR Power Consumption Oddity

    I have observed, what to me is, unexpected behavior in regards to the power consumption of the ZedBoard (Zynq-7000) when a processing core accesses the on board DDR memory in certain situations. I have performed a number of tests were I monitor the power consumption of either the A9 core with DDR or a softcore Microblaze with DDR. For both setups I have found cases where the power consumption of the board when actively running a program that frequently accesses DDR is lower than when the processor is sitting idle. This does not make sense to me as I would expect the power when active to be the power of the core + the power to access DDR versus just the power of the core when idle. I will describe a few of the cases I have tested and what I observed. In all cases the “active” execution is running a version of GUPS (giga updates per second), a program that repeatedly accesses a random location in a memory array of a controllable size. Microblaze connected to DDR through the AXI HP0 and HP1 ports of the Zynq A9. The local microblaze memory is only used for startup code. All other code and data is in DDR. Case 1: Microblaze with 32 kB I and D caches running GUPs with a 192MB working set. When execution is complete the processor is put to sleep using the “sleep” assembly instruction Observation 1a: With the I cache enabled and D cache disabled (meaning all accesses to the array to be updated should go to DDR) the board level power consumption is 7.2% *lower* when actively running than when put to sleep. Observation 1b: When both caches are disabled (meaning all accesses should go to DDR), power consumption is 4.7% *lower* when actively running than when put to sleep. Case 2: Microblaze with 32 kB I and D caches running GUPs with 4k working set (meaning it should fit within cache). When execution is complete the processor is put in a loop that continuously accesses the same index of the data array and sums it into a dummy variable. Observation 2a: With both caches disabled (meaning all accesses should go to DDR), power consumption is 10.6% *lower* in the busy wait than when actively running. Observation 2b: With both caches enabled (meaning most/all accesses should hit in caches), power consumption is 1.1% higher when actively running than when put to sleep. Zynq-7000 A9 connected to DDR. Case 3: A9 running GUPs with 384 MB working set (meaning most data accesses should go to DDR). When execution is complete the processor is put in idle loop similar to Case 2. Observation 3a: With caches enabled power consumption is 0.1% *lower* during active execution than when in busy wait. These observations are counter to a number of my expectations from traditional systems. Expectation 1: A running core that misses in the cache (or has not cache) and must frequently go to DDR should have higher power consumption than a sleeping core. The former has the power of both the core and DDR while the latter has just the power of a sleeping core (and basic DDR refresh). Observations 1a and 1b are counter to this expectation. Expectation 2: A core hitting in a local cache should consume less power than a core that has to frequently access DDR. Observations 2a, 2b, and 3a are all counter to this expectation. I am interested in two items related to the above observations: A potential explanation for the above observations (I have a few possibilities, but none are easy to verify) Is there some setup or configuration setting that would produce more expected behavior in terms of power consumption? Thanks.
  15. M. Z. Aziz Khan

    Power Supply by Analog Discovery 2

    I am a recent fan of Digilent. As a student I would like and recommend to have a fine measurement device like Analog Discovery 2 in combination to any digital/analog development. It provides a great insight into the working of your device, doesn’t matter either it is FPGA, Microcontroller based design, or purely Analog. One important point I would like to raise is that I have right now downloaded the Waveforms software of Analog Discovery 2 in order to see in detail that what it offers. I found that in the section of power supply, there is no option available to get 3.3V out of Analog Dicovery 2 to power our circuitry, rather we can get 3V or 4V. Since we know that many of the devices now a days work on 3.3V (like microcontrollers etc.) therefore I would suggest that it should be a must have option in the power supply options On best case, a user adjustable power supply option would be great Thanks
  16. Bought a new laptop with Windows 10 downloading original Waveforms to use with Discovery 1. It failed to recognize the devise. I removed waveform program and deleted any files relating to it and downloaded the new Waveforms 2015. This opened up but I got a message indicating that there was not enough power provided to the Discovery 1 devise. I tried using all USB ports which include USB 2.0 and 3.0 but had no such luck. Is there a fix for this issue?
  17. Greetings, New user to the forum, hope I can contribute some in the not so distant future. I am here by the recommendation of Digilent technical support. I am the new owner of a suspected malfunctioning Dev board (Genesys / Xilinx ) . Perhaps someone out there has some on hands experience with this particular product? I am having difficulty getting a power good indication (LD8) when I apply the required 5V supply. For a short time I have been exploring the Adept interface in an attempt to communicate with the board and when using the Power meter I notice the various voltages along with respected currents seem to be okay except the 2.5 V output indicates around 2 Volts and shows around -8 to -10 mA current. To me, this suggest no 2.5 V supply being generated by the switch mode power supply, are there any suggestions what to look for? So far, I have not had much success with email support in this matter. I really would like to get upto speed so I can contribute to the FPGA development community. Thank you in advance, J.L. Moon